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Searched refs:getVCC (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPeepholeSDWA.cpp1082 MISucc.substituteRegister(CarryIn->getReg(), TRI->getVCC(), 0, *TRI); in pseudoOpConvertToVOP2()
1110 MCRegister Vcc = TRI->getVCC(); in convertVcndmaskToVOP2()
1225 SDWAInst.addReg(TRI->getVCC(), RegState::Define); in createSDWAVersion()
H A DSIRegisterInfo.h394 MCRegister getVCC() const;
H A DSIPreEmitPeephole.cpp92 const unsigned CondReg = TRI->getVCC(); in optimizeVccBranch()
H A DSIInsertWaitcnts.cpp2564 TRI->getVCC()) in insertWaitcntInBlock()
2565 .addReg(TRI->getVCC()); in insertWaitcntInBlock()
H A DSIFoldOperands.cpp414 MRI->setRegAllocationHint(CarryOutReg, 0, TRI->getVCC()); in foldCopyToVGPROfScalarAddOfFrameIndex()
H A DSIInstrInfo.cpp7505 Register VCC = RI.getVCC(); in moveToVALUImpl()
9384 MRI.setRegAllocationHint(UnusedCarry, 0, RI.getVCC()); in getAddNoCarry()
9400 ? Register(RI.getVCC()) in getAddNoCarry()
H A DSIRegisterInfo.cpp3891 MCRegister SIRegisterInfo::getVCC() const { in getVCC() function in SIRegisterInfo
H A DAMDGPUISelDAGToDAG.cpp2600 Register CondReg = UseSCCBr ? AMDGPU::SCC : TRI->getVCC(); in SelectBRCOND()
H A DAMDGPUInstructionSelector.cpp3060 CondPhysReg = TRI.getVCC(); in selectG_BRCOND()
H A DSIISelLowering.cpp5747 I.addReg(TRI->getVCC(), RegState::Define); in EmitInstrWithCustomInserter()