| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 561 inline unsigned getUndefRegState(bool B) { in getUndefRegState() function 579 getUndefRegState(RegOp.isUndef()) | in getRegState()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineInstrBundle.cpp | 222 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) | in finalizeBundle()
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| H A D | SplitKit.cpp | 533 .addReg(ToReg, RegState::Define | getUndefRegState(FirstCopy) in buildSingleSubRegCopy()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 205 .addReg(CCReg, getUndefRegState(CC->isUndef()), CC->getSubReg()); in optimizeVcndVcmpPair()
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| H A D | AMDGPUInstructionSelector.cpp | 561 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef())); in selectG_MERGE_VALUES()
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| H A D | SIInstrInfo.cpp | 6315 unsigned VScalarOpUndef = getUndefRegState(ScalarOp->isUndef()); in emitLoadScalarOpsFromVGPRLoop()
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| H A D | SIISelLowering.cpp | 4492 .addReg(Idx.getReg(), getUndefRegState(Idx.isUndef())); in emitLoadM0FromVGPRLoop()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 1744 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR() 1752 .addReg(Reg, getKillRegState(RegDeadKill) | getUndefRegState(RegUndef)) in InsertLDR_STR() 1753 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR() 1823 getKillRegState(EvenDeadKill) | getUndefRegState(EvenUndef)) in FixInvalidRegPairOp() 1825 getKillRegState(OddDeadKill) | getUndefRegState(OddUndef)) in FixInvalidRegPairOp()
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| H A D | ARMExpandPseudoInsts.cpp | 720 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); in ExpandVST() 722 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); in ExpandVST() 724 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); in ExpandVST() 726 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); in ExpandVST() 804 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) | in ExpandLaneOp()
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| H A D | ARMBaseInstrInfo.cpp | 5215 .addReg(DReg, getUndefRegState(!MI.readsRegister(DReg, TRI))) in setExecutionDomain() 5251 .addReg(DDst, getUndefRegState(!MI.readsRegister(DDst, TRI))) in setExecutionDomain() 5285 NewMIB.addReg(CurReg, getUndefRegState(CurUndef)); in setExecutionDomain() 5289 NewMIB.addReg(CurReg, getUndefRegState(CurUndef)) in setExecutionDomain() 5303 MIB.addReg(CurReg, getUndefRegState(CurUndef)); in setExecutionDomain() 5307 MIB.addReg(CurReg, getUndefRegState(CurUndef)) in setExecutionDomain()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 681 unsigned Flags1 = getUndefRegState(Cond[1].isUndef()); in insertBranch() 685 unsigned Flags2 = getUndefRegState(Cond[2].isUndef()); in insertBranch() 696 unsigned Flags = getUndefRegState(RO.isUndef()); in insertBranch() 720 unsigned Flags = getUndefRegState(RO.isUndef()); in insertBranch() 926 unsigned UndefLo = getUndefRegState(!LiveAtMI.contains(SrcLo)); in copyPhysReg() 927 unsigned UndefHi = getUndefRegState(!LiveAtMI.contains(SrcHi)); in copyPhysReg() 1144 unsigned UndefLo = getUndefRegState(!LiveIn.contains(SrcLo)); in expandPostRAPseudo() 1145 unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi)); in expandPostRAPseudo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRExpandPseudoInsts.cpp | 1163 getKillRegState(DstIsKill) | getUndefRegState(DstIsUndef)) in expand() 1173 .addReg(DstReg, getUndefRegState(DstIsUndef)) in expand() 1177 .addReg(DstReg, getUndefRegState(DstIsUndef)) in expand() 1183 .addReg(DstReg, getUndefRegState(DstIsUndef)) in expand() 1188 .addReg(DstReg, getUndefRegState(DstIsUndef)) in expand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 84 unsigned Reg128Undef = getUndefRegState(LowRegOp.isUndef()); in splitMove() 281 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc)); in emitGRX32Move() 286 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc)) in emitGRX32Move()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegStackify.cpp | 655 .addReg(DefReg, getUndefRegState(DefMO.isDead())); in moveAndTeeForMultiUse()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 322 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)) in emitSPUpdate()
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| H A D | X86InstrInfo.cpp | 6071 MIB.addReg(MIB.getReg(1), getUndefRegState(MIB->getOperand(1).isUndef())); in expandSHXDROT() 8443 getUndefRegState(ImpOp.isUndef())); in unfoldMemoryOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 4993 .addReg(DestReg0, RegState::Define | getUndefRegState(IsUndef), SubIdx0) in loadRegPairFromStackSlot() 4994 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1) in loadRegPairFromStackSlot()
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