| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 2945 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2947 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
3101 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128, in LowerFNEGorFABS()
3103 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128, in LowerFNEGorFABS()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 3031 Base = CurDAG->getTargetInsertSubreg(X86::sub_32bit, DL, MVT::i64, ImplDef, in selectLEA64_32Addr()
3043 Index = CurDAG->getTargetInsertSubreg(X86::sub_32bit, DL, MVT::i64, ImplDef, in selectLEA64_32Addr()
4969 Src0 = CurDAG->getTargetInsertSubreg(SubReg, dl, CmpVT, ImplDef, Src0); in tryVPTESTM()
4972 Src1 = CurDAG->getTargetInsertSubreg(SubReg, dl, CmpVT, ImplDef, Src1); in tryVPTESTM()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 974 return CurDAG->getTargetInsertSubreg(SystemZ::subreg_l32, in convertTo()
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| H A D | SystemZISelLowering.cpp | 3853 In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL, in lowerBITCAST()
3866 SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL, in lowerBITCAST()
4265 return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL, in lowerOR()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 3129 SDValue NewIns = CurDAG->getTargetInsertSubreg( in tryInsertVectorElt()
3149 CurDAG->getTargetInsertSubreg(ARM::ssub_0 + Lane2 / 2, dl, MVT::v4f32, in tryInsertVectorElt()
3161 CurDAG->getTargetInsertSubreg(ARM::ssub_0 + Lane2 / 2, dl, MVT::v4f32, in tryInsertVectorElt()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAG.h | 1705 SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1195 return CurDAG->getTargetInsertSubreg(AArch64::sub_32, dl, MVT::i64, ImpDef, in Widen()
2269 return DAG.getTargetInsertSubreg(AArch64::dsub, DL, WideTy, Undef, V64Reg); in operator ()()
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| H A D | AArch64ISelLowering.cpp | 9979 DAG.getTargetInsertSubreg(Idx, DL, VecVT, DAG.getUNDEF(VecVT), In1); in LowerFCOPYSIGN()
9981 DAG.getTargetInsertSubreg(Idx, DL, VecVT, DAG.getUNDEF(VecVT), In2); in LowerFCOPYSIGN()
10765 TVal = DAG.getTargetInsertSubreg(AArch64::hsub, DL, MVT::f32, in LowerSELECT()
10767 FVal = DAG.getTargetInsertSubreg(AArch64::hsub, DL, MVT::f32, in LowerSELECT()
25842 Op = DAG.getTargetInsertSubreg(AArch64::hsub, DL, MVT::f32, in ReplaceBITCASTResults()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 2230 SDValue Insert = CurDAG->getTargetInsertSubreg(SubRegIdx, DL, VT, V, SubV); in Select()
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| H A D | RISCVISelLowering.cpp | 10176 DAG.getTargetInsertSubreg(SubRegIdx, DL, ContainerVecVT, Vec, SubVec); in lowerINSERT_SUBVECTOR()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 1386 return DAG.getTargetInsertSubreg(SubIdx, dl, VecTy, VecV, SubV); in insertHvxSubvectorReg()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 10956 SDValue SelectionDAG::getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT, in getTargetInsertSubreg() function in SelectionDAG
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