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Searched refs:getTII (Results 1 – 15 of 15) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizerCombiner.cpp89 BuildMI(MBB, InsertPt, DL, B.getTII().get(TargetOpcode::G_INTRINSIC)); in applySPIRVDistance()
H A DSPIRVCallLowering.cpp60 .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), in lowerReturn()
741 return MIB.constrainAllUses(MIRBuilder.getTII(), *ST->getRegisterInfo(), in lowerCall()
H A DSPIRVGlobalRegistry.cpp1827 MIRBuilder.getTII().get(SPIRV::OpTypePointer)) in getOrCreateSPIRVPointerTypeInternal()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRDFOpt.cpp218 auto &HII = static_cast<const HexagonInstrInfo&>(DFG.getTII()); in rewrite()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp1396 MI.setDesc(MIRBuilder.getTII().get(getRISCVWOpcode(MI.getOpcode()))); in legalizeCustom()
1409 MI.setDesc(MIRBuilder.getTII().get(getRISCVWOpcode(MI.getOpcode()))); in legalizeCustom()
1418 MI.setDesc(MIRBuilder.getTII().get(getRISCVWOpcode(MI.getOpcode()))); in legalizeCustom()
1426 MI.setDesc(MIRBuilder.getTII().get(getRISCVWOpcode(MI.getOpcode()))); in legalizeCustom()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp273 MI.setDesc(B.getTII().get(TargetOpcode::G_ZEXT)); in applyFoldMergeToZext()
301 MI.setDesc(B.getTII().get(TargetOpcode::G_ZEXT)); in applyMutateAnyExtToZExt()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp208 FromMI.setDesc(Builder.getTII().get(ToOpcode)); in replaceOpcodeWith()
874 MI.setDesc(Builder.getTII().get(LoadOpc)); in applyCombineExtendingLoads()
2096 MI.setDesc(MIB.getTII().get(TargetOpcode::G_SHL)); in applyCombineMulToShl()
2120 MI.setDesc(B.getTII().get(TargetOpcode::G_ADD)); in matchCombineSubToAdd()
2888 if (Builder.getTII().produceSameValue(*I1, *I2, &MRI)) { in matchEqualDefs()
3640 Def->setDesc(Builder.getTII().get(TargetOpcode::G_OR)); in applyNotCmp()
3643 Def->setDesc(Builder.getTII().get(TargetOpcode::G_AND)); in applyNotCmp()
3691 MI.setDesc(Builder.getTII().get(TargetOpcode::G_AND)); in applyXorOfAndWithSameReg()
4198 if (Builder.getTII().isExtendLikelyToBeFolded(*ExtMI, MRI)) in matchExtendThroughPhis()
4463 MI.setDesc(Builder.getTII().get(IsFSHL ? TargetOpcode::G_ROTL in applyFunnelShiftToRotate()
[all …]
H A DMachineIRBuilder.cpp42 getTII().get(Opcode)); in buildInstrNoInsert()
60 getTII().get(TargetOpcode::DBG_VALUE), in buildDirectDbgValue()
73 getTII().get(TargetOpcode::DBG_VALUE), in buildIndirectDbgValue()
H A DLegalizerHelper.cpp594 isLibCallInTailPosition(Result, *MI, MIRBuilder.getTII(), in createLibcall()
753 << MIRBuilder.getTII().getName(Opc) << "\n"); in createMemLibcall()
763 isLibCallInTailPosition(Info.OrigRet, MI, MIRBuilder.getTII(), MRI); in createMemLibcall()
903 << MIRBuilder.getTII().getName(Opc) << "\n"); in createAtomicLibcall()
3390 MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::G_BUILD_VECTOR_TRUNC)); in widenScalar()
4421 MI.setDesc(MIRBuilder.getTII().get(NewOpcode)); in changeOpcode()
4466 const auto &TII = MIRBuilder.getTII(); in lower()
7090 const auto &TII = MIRBuilder.getTII(); in lowerBitCount()
9561 MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::COPY)); in lowerVectorReduction()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsLegalizerInfo.cpp477 .constrainAllUses(MIRBuilder.getTII(), *ST.getRegisterInfo(), in SelectMSA3OpIntrinsic()
H A DMipsCallLowering.cpp543 MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), in lowerCall()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRDFGraph.h695 const TargetInstrInfo &getTII() const { return TII; } in getTII() function
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2374 MI.setDesc(B.getTII().get(TargetOpcode::G_BITCAST)); in legalizeAddrSpaceCast()
4326 Register LiveIn = getFunctionLiveInPhysReg(B.getMF(), B.getTII(), SrcReg, in buildLoadInputValue()
6518 MI.setDesc(B.getTII().get(NewOpcode)); in legalizeImageIntrinsic()
6884 MI.setDesc(B.getTII().get(Opc)); in legalizeSBufferLoad()
6922 MI.setDesc(B.getTII().get(AMDGPU::G_AMDGPU_S_BUFFER_PREFETCH)); in legalizeSBufferPrefetch()
6948 BuildMI(BB, BB.end(), DL, B.getTII().get(AMDGPU::S_ENDPGM)) in legalizeTrapEndpgm()
6960 BuildMI(*TrapBB, TrapBB->end(), DL, B.getTII().get(AMDGPU::S_ENDPGM)) in legalizeTrapEndpgm()
6962 BuildMI(BB, &MI, DL, B.getTII().get(AMDGPU::S_CBRANCH_EXECNZ)) in legalizeTrapEndpgm()
7654 MI.setDesc(B.getTII().get(AMDGPU::G_AMDGPU_FMED3)); in legalizeIntrinsic()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h282 const TargetInstrInfo &getTII() { in getTII() function
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRDFGraph.cpp226 OS << Print(P.Obj.Id, P.G) << ": " << P.G.getTII().getName(Opc); in operator <<()