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Searched refs:getSubRegs (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td43 class getSubRegs<int size> {
381 def SGPR_64Regs : SIRegisterTuples<getSubRegs<2>.ret, SGPR_32, 105, 2, 2, "s">;
384 def SGPR_96Regs : SIRegisterTuples<getSubRegs<3>.ret, SGPR_32, 105, 4, 3, "s">;
387 def SGPR_128Regs : SIRegisterTuples<getSubRegs<4>.ret, SGPR_32, 105, 4, 4, "s">;
390 def SGPR_160Regs : SIRegisterTuples<getSubRegs<5>.ret, SGPR_32, 105, 4, 5, "s">;
393 def SGPR_192Regs : SIRegisterTuples<getSubRegs<6>.ret, SGPR_32, 105, 4, 6, "s">;
396 def SGPR_224Regs : SIRegisterTuples<getSubRegs<7>.ret, SGPR_32, 105, 4, 7, "s">;
399 def SGPR_256Regs : SIRegisterTuples<getSubRegs<8>.ret, SGPR_32, 105, 4, 8, "s">;
402 def SGPR_288Regs : SIRegisterTuples<getSubRegs<9>.ret, SGPR_32, 105, 4, 9, "s">;
405 def SGPR_320Regs : SIRegisterTuples<getSubRegs<10>.ret, SGPR_32, 105, 4, 10, "s">;
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp119 void getSubRegs(unsigned Reg, BitVector &SRs) const;
138 void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const { in getSubRegs() function in HexagonGenMux
145 getSubRegs(Reg, Set); in expandReg()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp1222 for (auto [SRI, SR] : Reg.getSubRegs()) { in CodeGenRegBank()
1406 const CodeGenRegister::SubRegMap &SM = R.getSubRegs(); in computeComposites()
1458 const CodeGenRegister::SubRegMap &SRM1 = Reg1.getSubRegs(); in computeComposites()
1463 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); in computeComposites()
1852 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs(); in normalizeWeight()
2168 const SubRegMap &SubRegs = Register.getSubRegs(); in computeRegUnitLaneMasks()
2172 if (!SubReg->getSubRegs().empty()) in computeRegUnitLaneMasks()
2293 const CodeGenRegister::SubRegMap &SRM = R->getSubRegs(); in inferSubClassWithSubReg()
2357 const CodeGenRegister *Sub = Super->getSubRegs().find(SubIdx)->second; in inferMatchingSuperRegClass()
2633 const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs(); in computeCoveredRegisters()
H A DCodeGenRegisters.h208 const SubRegMap &getSubRegs() const { in getSubRegs() function
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp1933 for (auto &[SubIdx, SubReg] : R.getSubRegs()) { in debugDump()