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Searched refs:getSubRegisterClass (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DInitUndef.cpp177 return !TRI->getSubRegisterClass(TargetRegClass, Ind); in handleSubReg()
185 TRI->getSubRegisterClass(TargetRegClass, ind); in handleSubReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp309 TRI.getSubRegisterClass(RC, MO.getSubReg())) in getRegOpRC()
1031 const TargetRegisterClass *RC64 = TRI->getSubRegisterClass( in isRegSeqSplat()
1065 OpRC = TRI->getSubRegisterClass(OpRC, AMDGPU::sub0); in tryFoldRegSeqSplat()
1068 OpRC = TRI->getSubRegisterClass(OpRC, AMDGPU::sub0_sub1); in tryFoldRegSeqSplat()
1424 TRI->getSubRegisterClass(RC, SubReg)) in foldOperand()
1901 TRI->getSubRegisterClass(UseRC, DestSubIdx); in foldCopyToAGPRRegSequence()
1910 if (TRI->getSubRegisterClass(MRI->getRegClass(Src.Reg), Src.SubReg) != in foldCopyToAGPRRegSequence()
2489 if (const auto *SubRC = TRI->getSubRegisterClass(CopyInRC, AGPRRegMask)) in tryFoldPhiAGPR()
H A DGCNRewritePartialRegUses.cpp218 auto *SubRegRC = TRI->getSubRegisterClass(RC, OldSubReg); in getRegClassWithShiftedSubregs()
H A DSIInstrInfo.cpp4915 RI.getSubRegisterClass(RC, MO.getSubReg())) { in verifyInstruction()
8284 RI.getSubRegisterClass(Src0RC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
8292 RI.getSubRegisterClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
8346 RI.getSubRegisterClass(Src0RC, AMDGPU::sub0); in splitScalarSMulU64()
8350 RI.getSubRegisterClass(Src1RC, AMDGPU::sub0); in splitScalarSMulU64()
8455 RI.getSubRegisterClass(Src0RC, AMDGPU::sub0); in splitScalarSMulPseudo()
8459 RI.getSubRegisterClass(Src1RC, AMDGPU::sub0); in splitScalarSMulPseudo()
8518 RI.getSubRegisterClass(Src0RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
8524 RI.getSubRegisterClass(Src1RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
8538 RI.getSubRegisterClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
[all …]
H A DSIRegisterInfo.cpp3707 return getSubRegisterClass(SrcRC, MO.getSubReg()); in getRegClassForOperandReg()
H A DSIISelLowering.cpp5419 TRI->getSubRegisterClass(Src0RC, AMDGPU::sub0); in EmitInstrWithCustomInserter()
5421 TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter()
5508 TRI->getSubRegisterClass(Src2RC, AMDGPU::sub0); in EmitInstrWithCustomInserter()
5661 TRI->getSubRegisterClass(Src0RC, AMDGPU::sub0); in EmitInstrWithCustomInserter()
5663 TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp741 TRI->getSubRegisterClass(DstRC64, AArch64::sub_32); in visitUBFMXri()
748 TRI->getSubRegisterClass(SrcRC64, AArch64::sub_32); in visitUBFMXri()
H A DAArch64LoadStoreOptimizer.cpp1709 (TRI->getSubRegisterClass(RegClass, AArch64::dsub0) || in canRenameMOP()
1710 TRI->getSubRegisterClass(RegClass, AArch64::qsub0) || in canRenameMOP()
1711 TRI->getSubRegisterClass(RegClass, AArch64::zsub0))) { in canRenameMOP()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h710 getSubRegisterClass(const TargetRegisterClass *SuperRC, in getSubRegisterClass() function