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Searched refs:getSubRegIndexLaneMask (Results 1 – 25 of 32) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp173 MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx); in transferUsedLanes()
234 DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
241 DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
245 DefinedLanes &= ~TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
369 UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg); in determineInitialUsedLanes()
427 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg); in isUndefRegAtInput()
H A DLiveIntervalCalc.cpp59 LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) in calculate()
159 LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg); in extendToUses()
H A DTargetRegisterInfo.cpp574 LaneBitmask SubRegMask = getSubRegIndexLaneMask(Idx); in getCoveringSubRegIndexes()
601 LaneBitmask LanesLeft = LaneMask & ~getSubRegIndexLaneMask(BestIdx); in getCoveringSubRegIndexes()
606 LaneBitmask SubRegMask = getSubRegIndexLaneMask(Idx); in getCoveringSubRegIndexes()
632 LanesLeft &= ~getSubRegIndexLaneMask(BestIdx); in getCoveringSubRegIndexes()
H A DLiveRangeEdit.cpp141 LaneBitmask LM = SubReg ? TRI->getSubRegIndexLaneMask(SubReg) in allUsesAvailableAt()
270 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg); in useIsKill()
405 Alloc, TRI->getSubRegIndexLaneMask(DestSubReg)); in eliminateDeadDef()
H A DRegisterCoalescer.cpp1554 LaneBitmask UsedLanes = TRI->getSubRegIndexLaneMask(NewIdx); in reMaterializeTrivialDef()
1603 LaneBitmask DstMask = TRI->getSubRegIndexLaneMask(NewIdx); in reMaterializeTrivialDef()
1747 LaneBitmask SrcMask = TRI->getSubRegIndexLaneMask(SrcSubIdx); in eliminateUndefCopy()
1795 LaneBitmask DstMask = TRI->getSubRegIndexLaneMask(DstSubIdx); in eliminateUndefCopy()
1814 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg()); in eliminateUndefCopy()
1849 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubRegIdx); in addUndefFlag()
1935 LaneBitmask UsedLanes = TRI->getSubRegIndexLaneMask(SubIdx); in updateRegDefsUses()
2009 LaneBitmask SubRegMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in setUndefOnPrunedSubRegUses()
2586 ValidLanes = TRI.getSubRegIndexLaneMask(ImpDef.getOperand(0).getSubReg()); in mustKeepImplicitDef()
2716 L |= TRI->getSubRegIndexLaneMask( in computeWriteLanes()
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H A DLiveIntervals.cpp602 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg); in shrinkToUses()
828 LaneBitmask UseMask = SubReg ? TRI->getSubRegIndexLaneMask(SubReg) in addKillFlags()
1078 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg) in updateAllRanges()
1095 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg) in updateAllRanges()
1513 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask).none()) in findLastUseBefore()
1646 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg); in repairOldRegInRange()
1741 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg); in repairIntervalsInRange()
H A DRenameIndependentSubregs.cpp189 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findComponents()
233 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in rewriteOperands()
H A DPeepholeOptimizer.cpp1986 LaneBitmask DefMask = TRI->getSubRegIndexLaneMask(DefSubReg); in getNextSourceFromRegSequence()
1987 LaneBitmask ThisOpRegMask = TRI->getSubRegIndexLaneMask(RegSeqInput.SubIdx); in getNextSourceFromRegSequence()
2057 if ((TRI->getSubRegIndexLaneMask(DefSubReg) & in getNextSourceFromInsertSubreg()
2058 TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)) in getNextSourceFromInsertSubreg()
H A DVirtRegMap.cpp468 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in readsUndefSubreg()
611 LaneBitmask UndefMask = ~TRI->getSubRegIndexLaneMask(SubReg); in liveOutUndefPhiLanesForUndefSubregDef()
H A DMachineInstrBundle.cpp302 LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(SubReg); in AnalyzeVirtRegLanesInBundle()
H A DLivePhysRegs.cpp167 if ((Mask & TRI->getSubRegIndexLaneMask(SI)).any()) in addBlockLiveIns()
H A DTwoAddressInstructionPass.cpp1684 RemainingUses |= TRI->getSubRegIndexLaneMask(MO.getSubReg()); in processTiedPairs()
1938 TRI->getSubRegIndexLaneMask(mi->getOperand(0).getSubReg()); in run()
2010 UndefLanes |= TRI->getSubRegIndexLaneMask(SubIdx); in eliminateRegSequence()
2071 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg); in eliminateRegSequence()
H A DLiveInterval.cpp898 LaneBitmask OrigMask = TRI.getSubRegIndexLaneMask(MOI->getSubReg()); in stripValuesNotDefiningMask()
978 LaneBitmask DefMask = TRI.getSubRegIndexLaneMask(SubReg); in computeSubRangeUndefs()
H A DRegisterPressure.cpp550 ? TRI.getSubRegIndexLaneMask(SubRegIdx) in pushRegLanes()
1224 LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findUseBetween()
H A DMachineVerifier.cpp2999 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
3102 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
3616 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none()) in verifyLiveRangeValue()
3749 Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub) : LaneBitmask::getAll(); in verifyLiveRangeSegment()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFormMemoryClauses.cpp181 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(MO.getSubReg()); in canBundle()
233 ? TRI->getSubRegIndexLaneMask(MO.getSubReg()) in collectRegUses()
H A DGCNRewritePartialRegUses.cpp346 return SR.LaneMask == TRI->getSubRegIndexLaneMask(P.first); in updateLiveIntervals()
376 TRI->getSubRegIndexLaneMask(NewSubReg), SR); in updateLiveIntervals()
H A DGCNRegPressure.cpp263 MRI.getTargetRegisterInfo()->getSubRegIndexLaneMask(MO.getSubReg()); in getDefRegMask()
287 P.LaneMask |= MO.getSubReg() ? TRI.getSubRegIndexLaneMask(MO.getSubReg()) in collectVirtualRegUses()
356 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in findUseBetween()
H A DSIRegisterInfo.h429 return getNumCoveredRegs(getSubRegIndexLaneMask(SubReg)); in getNumChannelsFromSubReg()
H A DSIShrinkInstructions.cpp618 LaneBitmask Overlap = TRI->getSubRegIndexLaneMask(SubReg) & in instAccessReg()
619 TRI->getSubRegIndexLaneMask(MO.getSubReg()); in instAccessReg()
H A DSIRegisterInfo.cpp334 assert(getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() == 3 && in SIRegisterInfo()
335 getSubRegIndexLaneMask(AMDGPU::sub31).getAsInteger() == (3ULL << 62) && in SIRegisterInfo()
336 (getSubRegIndexLaneMask(AMDGPU::lo16) | in SIRegisterInfo()
337 getSubRegIndexLaneMask(AMDGPU::hi16)).getAsInteger() == in SIRegisterInfo()
338 getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() && in SIRegisterInfo()
3932 LaneBitmask SubLanes = SubReg ? getSubRegIndexLaneMask(SubReg) in findReachingDef()
H A DSIWholeQuadMode.cpp339 SubReg ? TRI->getSubRegIndexLaneMask(SubReg) in markDefs()
401 : TRI->getSubRegIndexLaneMask(Op.getSubReg()); in markDefs()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DRDFCopy.cpp164 if (RR.Mask == TRI.getSubRegIndexLaneMask(S.getSubRegIndex())) in run()
H A DHexagonBlockRanges.cpp245 if ((I.LaneMask & TRI.getSubRegIndexLaneMask(SI)).any()) in getLiveIns()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h422 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask() function

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