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Searched refs:getSpillSize (Results 1 – 25 of 46) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp50 LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true); in createLRSpillSlot()
52 LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), in createLRSpillSlot()
67 MFI.CreateStackObject(TRI.getSpillSize(RC), TRI.getSpillAlign(RC), true); in createFPSpillSlot()
79 unsigned Size = TRI.getSpillSize(RC); in createEHSpillSlot()
H A DXCoreFrameLowering.cpp576 unsigned Size = TRI.getSpillSize(RC); in processFunctionBeforeFrameFinalized()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp165 I = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC), in createEhDataRegsFI()
179 I = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC), in createISRRegFI()
206 TRI.getSpillSize(*RC), TRI.getSpillAlign(*RC), false); in getMoveF64ViaSpillFI()
H A DMipsFrameLowering.cpp121 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R)); in estimateStackSize()
H A DMipsSEFrameLowering.cpp860 int FI = MF.getFrameInfo().CreateSpillStackObject(TRI->getSpillSize(RC), in determineCalleeSaves()
876 int FI = MF.getFrameInfo().CreateSpillStackObject(TRI->getSpillSize(RC), in determineCalleeSaves()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86LowerTileCopy.cpp101 unsigned Size = TRI->getSpillSize(X86::TILERegClass); in runOnMachineFunction()
124 Size = TRI->getSpillSize(X86::GR64RegClass); in runOnMachineFunction()
H A DX86FastPreTileConfig.cpp126 unsigned Size = TRI->getSpillSize(RC); in getStackSpaceFor()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp794 switch (TRI->getSpillSize(*RC)) { in getLoadStoreRegOpcode()
799 << " with spill size " << TRI->getSpillSize(*RC) << '\n'); in getLoadStoreRegOpcode()
845 assert(MFI.getObjectSize(FrameIndex) >= TRI->getSpillSize(*RC) && in storeRegToStackSlot()
864 assert(MFI.getObjectSize(FrameIndex) >= TRI->getSpillSize(*RC) && in loadRegFromStackSlot()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp309 assert(TRI->getSpillSize(*RC) == 4 && in storeRegToStackSlot()
338 assert(TRI->getSpillSize(*RC) == 4 && in loadRegFromStackSlot()
H A DARCFrameLowering.cpp441 int RegScavFI = MFI.CreateSpillStackObject(RegInfo->getSpillSize(*RC), in processFunctionBeforeFrameFinalized()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonVExtract.cpp141 int FI = MFI.CreateStackObject(HRI.getSpillSize(VecRC), Alignment, in runOnMachineFunction()
H A DHexagonFrameLowering.cpp1655 int FI = MFI.CreateFixedSpillStackObject(TRI->getSpillSize(*RC), S->Offset); in assignCalleeSavedSpillSlots()
1667 unsigned Size = TRI->getSpillSize(*RC); in assignCalleeSavedSpillSlots()
1891 unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass); in expandStoreVec2()
1938 unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass); in expandLoadVec2()
2108 unsigned S = HRI.getSpillSize(*RC); in determineCalleeSaves()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp711 CalleeSavedSize += getSpillSize(RISCV::GPRRegClass); in needsFrameBaseReg()
713 CalleeSavedSize += getSpillSize(RISCV::FPR64RegClass); in needsFrameBaseReg()
715 CalleeSavedSize += getSpillSize(RISCV::FPR32RegClass); in needsFrameBaseReg()
H A DRISCVFrameLowering.cpp244 int FI = MFI.CreateStackObject(TRI.getSpillSize(RC), TRI.getSpillAlign(RC), in createSiFivePreemptibleInterruptFrameEntries()
1759 int FI = MFI.CreateSpillStackObject(RegInfo->getSpillSize(*RC), in processFunctionBeforeFrameFinalized()
1954 unsigned Size = RegInfo->getSpillSize(*RC); in assignCalleeSavedSpillSlots()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DStackMaps.cpp283 Locs.emplace_back(Location::Register, TRI->getSpillSize(*RC), in parseOperand()
369 unsigned Size = TRI->getSpillSize(*TRI->getMinimalPhysRegClass(Reg)); in createLiveOutReg()
H A DRegisterScavenging.cpp229 unsigned NeedSize = TRI->getSpillSize(RC); in spill()
H A DFixupStatepointCallerSaved.cpp99 return TRI.getSpillSize(*RC); in getRegisterSize()
H A DTargetInstrInfo.cpp428 Size = TRI->getSpillSize(*RC); in getStackSlotRange()
444 assert(TRI->getSpillSize(*RC) >= (Offset + Size) && "bad subregister range"); in getStackSlotRange()
447 Offset = TRI->getSpillSize(*RC) - (Offset + Size); in getStackSlotRange()
H A DVirtRegMap.cpp97 unsigned Size = TRI->getSpillSize(*RC); in createSpillSlot()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaFrameLowering.cpp380 unsigned Size = TRI->getSpillSize(RC); in processFunctionBeforeFrameFinalized()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp3301 int Scale = TRI->getSpillSize(*RPI.RC); in computeCalleeSaveRegisterPairs()
3516 unsigned Size = TRI->getSpillSize(*RPI.RC); in spillCalleeSavedRegisters()
3746 unsigned Size = TRI->getSpillSize(*RPI.RC); in restoreCalleeSavedRegisters()
4002 if (RegInfo->getSpillSize(AArch64::PPRRegClass) == 16 && in determineCalleeSaves()
4058 auto SpillSize = TRI->getSpillSize(*RC); in determineCalleeSaves()
4166 unsigned Size = TRI->getSpillSize(RC); in determineCalleeSaves()
4279 unsigned Size = RegInfo->getSpillSize(*RC); in assignCalleeSavedSpillSlots()
4506 *MaybeSpillFI = MFI.CreateSpillStackObject(TRI.getSpillSize(RC), in ScopedScavengeOrSpill()
4727 if (AFI->hasStackFrame() && TRI.getSpillSize(AArch64::PPRRegClass) == 16) { in processFunctionBeforeFrameFinalized()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFrameLowering.cpp176 MFI.CreateSpillStackObject(RI->getSpillSize(RC), RI->getSpillAlign(RC)); in processFunctionBeforeFrameFinalized()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILowerSGPRSpills.cpp272 int JunkFI = MFI.CreateStackObject(TRI->getSpillSize(*RC), in spillCalleeSavedRegs()
H A DSIFrameLowering.cpp81 unsigned Size = TRI->getSpillSize(RC); in getVGPRSpillLaneOrTempRegister()
1677 MFI->allocateWWMSpill(MF, Reg, TRI->getSpillSize(*RC), in determineCalleeSaves()
1812 unsigned BlockSize = TRI->getSpillSize(*BlockRegClass) - UnusedBits * 4; in assignSlotsUsingVGPRBlocks()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h302 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize() function

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