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Searched refs:getSchedClass (Results 1 – 25 of 33) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp98 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps()
123 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass()
190 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
246 unsigned SCIdx = TII->get(Opcode).getSchedClass(); in computeInstrLatency()
311 unsigned SchedClass = MI->getDesc().getSchedClass(); in computeReciprocalThroughput()
324 unsigned SchedClass = TII->get(Opcode).getSchedClass(); in computeReciprocalThroughput()
H A DDFAPacketizer.cpp56 unsigned Action = ItinActions[MID->getSchedClass()]; in canReserveResources()
57 if (MID->getSchedClass() == 0 || Action == 0) in canReserveResources()
65 unsigned Action = ItinActions[MID->getSchedClass()]; in reserveResources()
66 if (MID->getSchedClass() == 0 || Action == 0) in reserveResources()
H A DScoreboardHazardRecognizer.cpp127 unsigned idx = MCID->getSchedClass(); in getHazardType()
186 unsigned idx = MCID->getSchedClass(); in EmitInstruction()
H A DTargetInstrInfo.cpp1451 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass(); in getOperandLatency()
1454 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass(); in getOperandLatency()
1466 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass()); in getInstrLatency()
1478 unsigned Class = MI.getDesc().getSchedClass(); in getNumMicroOps()
1512 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); in getInstrLatency()
1522 unsigned DefClass = DefMI.getDesc().getSchedClass(); in hasLowDefLatency()
1646 unsigned DefClass = DefMI.getDesc().getSchedClass(); in getOperandLatency()
1647 unsigned UseClass = UseMI.getDesc().getSchedClass(); in getOperandLatency()
H A DMachineScheduler.cpp1015 const MCSchedClassDesc *SC = getSchedClass(SU); in dumpScheduleTraceTopDown()
1046 const MCSchedClassDesc *SC = getSchedClass(SU); in dumpScheduleTraceTopDown()
1097 const MCSchedClassDesc *SC = getSchedClass(SU); in dumpScheduleTraceBottomUp()
1128 const MCSchedClassDesc *SC = getSchedClass(SU); in dumpScheduleTraceBottomUp()
2288 const MCSchedClassDesc *SC = DAG->getSchedClass(&SU); in init()
2479 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in checkHazard()
2692 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in bumpNode()
2978 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in initResourceDelta()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp47 const MCSchedClassDesc *SC = getSchedClass(SU); in getNumDecoderSlots()
93 const MCSchedClassDesc *SC = getSchedClass(SU); in fitsIntoCurrentGroup()
171 const MCSchedClassDesc *SC = getSchedClass(SU); in dumpSU()
272 const MCSchedClassDesc *SC = getSchedClass(SU); in EmitInstruction()
341 const MCSchedClassDesc *SC = getSchedClass(SU); in groupingCost()
390 const MCSchedClassDesc *SC = getSchedClass(SU); in resourcesCost()
H A DSystemZHazardRecognizer.h121 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass() function
H A DSystemZMachineScheduler.cpp254 const MCSchedClassDesc *SC = HazardRec->getSchedClass(SU); in releaseTopNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp86 unsigned SCIdx = TII->get(AArch64::STPDi).getSchedClass(); in shouldAddSTPToBlock()
90 unsigned SCIdx2 = TII->get(AArch64::STRDui).getSchedClass(); in shouldAddSTPToBlock()
H A DAArch64SIMDInstrOpt.cpp229 unsigned SCIdx = InstDesc->getSchedClass(); in shouldReplaceInst()
244 IDesc->getSchedClass()); in shouldReplaceInst()
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp72 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in computeInstrLatency()
115 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in getReciprocalThroughput()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/
H A DRISCVCustomBehaviour.cpp224 unsigned SchedClassID = MCII.get(Opcode).getSchedClass(); in getSchedClassID()
281 return MCII.get(RVV->Pseudo).getSchedClass(); in getSchedClassID()
/freebsd/contrib/llvm-project/llvm/lib/MCA/
H A DCustomBehaviour.cpp58 return MCII.get(MCI.getOpcode()).getSchedClass(); in getSchedClassID()
/freebsd/contrib/llvm-project/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp181 unsigned SCClass = Desc.getSchedClass(); in getItineraryLatency()
209 unsigned SCClass = Desc.getSchedClass(); in getLatency()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp66 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR) in isBCTRAfterSet()
90 unsigned IIC = MCID->getSchedClass(); in mustComeFirst()
/freebsd/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DInstructionInfoView.cpp125 ? MCDesc.getSchedClass() in collectData()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenSchedule.h543 CodeGenSchedClass &getSchedClass(unsigned Idx) { in getSchedClass() function
547 const CodeGenSchedClass &getSchedClass(unsigned Idx) const { in getSchedClass() function
H A DCodeGenSchedule.cpp916 CodeGenSchedClass &SC = getSchedClass(SCIdx); in collectSchedClasses()
1665 << SchedModels.getSchedClass(SCTrans.ToClassIdx).Name << "(" in dumpTransition()
1690 const CodeGenSchedClass &FromSC = SchedModels.getSchedClass(FromClassIdx); in inferFromTransitions()
1705 SchedModels.getSchedClass(FromClassIdx) in inferFromTransitions()
2000 const CodeGenSchedClass &SC = getSchedClass(SCIdx); in checkCompleteness()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp654 << ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n"; in EmitItineraries()
1425 assert(SchedModels.getSchedClass(0).Name == "NoInstrModel" && in EmitSchedClassTables()
1433 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx); in EmitSchedClassTables()
1701 const CodeGenSchedClass &SC = SchedModels.getSchedClass(VC); in emitSchedModelHelpersImpl()
1743 emitPredicates(T, SchedModels.getSchedClass(T.ToClassIdx), PE, OS); in emitSchedModelHelpersImpl()
1746 emitPredicates(*FinalT, SchedModels.getSchedClass(FinalT->ToClassIdx), in emitSchedModelHelpersImpl()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupInstTuning.cpp90 *ST, *(SM->getSchedClassDesc(TII->get(Opcode).getSchedClass()))); in processInstruction()
96 *ST, *(SM->getSchedClassDesc(TII->get(Opcode).getSchedClass()))); in processInstruction()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrDesc.h600 unsigned getSchedClass() const { return SchedClass; }
601 unsigned getSchedClass() const { return SchedClass; } getSchedClass() function
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScheduleDAGInstrs.h272 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass() function
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp435 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getCVIResources()
454 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getUnits()
465 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getOtherReservedSlots()
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/
H A DInstruction.h362 unsigned getSchedClass() const { return RD->SchedClassID; } in getSchedClass() function
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp2667 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC1()
2672 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC2()
2677 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC2Early()
2682 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC4x()
4316 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); in getInstrTimingClassLatency()
4622 const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass()); in getUnits()
4689 << " Class: " << NewMI->getDesc().getSchedClass()); in genAllInsnTimingClasses()

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