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Searched refs:getSGPRClassForBitWidth (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h195 static const TargetRegisterClass *getSGPRClassForBitWidth(unsigned BitWidth);
H A DSIRegisterInfo.cpp2835 SIRegisterInfo::getSGPRClassForBitWidth(unsigned BitWidth) { in getSGPRClassForBitWidth() function in SIRegisterInfo
2901 const TargetRegisterClass *SRC = getSGPRClassForBitWidth(Size); in getEquivalentSGPRClass()
3105 return getSGPRClassForBitWidth(std::max(32u, Size)); in getRegClassForSizeOnBank()
H A DAMDGPULegalizerInfo.cpp154 if (SIRegisterInfo::getSGPRClassForBitWidth(NewNumElts * EltSize)) in moreElementsToNextExistingRegClass()
268 !SIRegisterInfo::getSGPRClassForBitWidth(Ty.getSizeInBits()); in isIllegalRegisterType()
1773 !!SIRegisterInfo::getSGPRClassForBitWidth(VecTy.getSizeInBits()); in AMDGPULegalizerInfo()
H A DAMDGPUISelDAGToDAG.cpp565 SIRegisterInfo::getSGPRClassForBitWidth(NumVectorElts * 32)->getID(); in Select()
H A DSIISelLowering.cpp2552 TRI.getSGPRClassForBitWidth(NumAllocSGPRs * 32); in allocatePreloadKernArgSGPRs()
15378 RC = SIRegisterInfo::getSGPRClassForBitWidth(BitWidth); in getRegForInlineAsmConstraint()
15442 RC = TRI->getSGPRClassForBitWidth(Width); in getRegForInlineAsmConstraint()