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Searched refs:getResNo (Results 1 – 25 of 39) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSDNodeDbgValue.h49 unsigned getResNo() const { in getResNo() function
91 return getSDNode() == Other.getSDNode() && getResNo() == Other.getResNo();
H A DSelectionDAGPrinter.cpp64 std::advance(NI, I.getNode()->getOperand(I.getOperand()).getResNo()); in getEdgeTarget()
131 GW.emitEdge(nullptr, -1, G->getRoot().getNode(), G->getRoot().getResNo(), in addCustomGraphFeatures()
H A DScheduleDAGSDNodes.cpp126 unsigned ResNo = User->getOperand(2).getResNo(); in CheckForPhysRegDependency()
241 if (I.getUse().getResNo() != Chain.getResNo()) in ClusterNeighboringLoads()
479 unsigned DefIdx = N->getOperand(i).getResNo(); in AddSchedEdges()
658 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency()
748 VRBaseMap.count({L.getSDNode(), L.getResNo()}) == 0) in ProcessSDDbgValues()
H A DResourcePriorityQueue.cpp131 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU()
335 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in rawRegPressureDelta()
485 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in scheduledNode()
H A DInstrEmitter.cpp112 User->getOperand(2).getResNo() == ResNo) { in EmitCopyFromReg()
122 if (Op.getNode() != Node || Op.getResNo() != ResNo) in EmitCopyFromReg()
124 MVT VT = Node->getSimpleValueType(Op.getResNo()); in EmitCopyFromReg()
231 User->getOperand(2).getResNo() == i) { in CreateVirtualRegisters()
764 SDValue V = SDValue(Op.getSDNode(), Op.getResNo()); in AddDbgValueLocationOps()
860 SDValue Op = SDValue(Node, DbgOperand.getResNo()); in EmitDbgInstrRef()
H A DSelectionDAG.cpp722 ID.AddInteger(Op.getResNo()); in AddNodeIDOperands()
731 ID.AddInteger(Op.getResNo()); in AddNodeIDOperands()
2555 unsigned ResNo = StoreValue.getResNo(); in expandMultipleResultFPLibCall()
3417 return computeKnownBits(Op.getOperand(Op.getResNo()), DemandedElts, in computeKnownBits()
3735 assert((Op.getResNo() == 0 || Op.getResNo() == 1) && "Unknown result"); in computeKnownBits()
3739 if (Op.getResNo() == 0) in computeKnownBits()
3746 assert((Op.getResNo() == 0 || Op.getResNo() == 1) && "Unknown result"); in computeKnownBits()
3750 if (Op.getResNo() == 0) in computeKnownBits()
3803 if (Op.getResNo() != 1) in computeKnownBits()
3894 assert((Op.getResNo() == 0 || Op.getResNo() == 1) && "Unknown result"); in computeKnownBits()
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H A DSelectionDAGAddressAnalysis.cpp245 if (LSBase->isIndexed() && Base.getResNo() == IndexResNo) in matchLSNode()
H A DSelectionDAGDumper.cpp1002 OS << "SDNODE=" << PrintNodeId(*Op.getSDNode()) << ':' << Op.getResNo(); in print()
1111 if (unsigned RN = Value.getResNo()) in printOperand()
H A DSelectionDAGBuilder.cpp981 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), &Parts[Part], in getCopyToRegs()
1212 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(), in handleDebugDeclare()
1640 SDDbgOperand::fromNode(N.getNode(), N.getResNo())); in handleDebugValue()
2183 SDValue Val = RetOp.getValue(RetOp.getResNo() + i); in visitRet()
2229 SDValue(RetOp.getNode(), RetOp.getResNo() + j), in visitRet()
3857 EVT VT = LHSVal.getNode()->getValueType(LHSVal.getResNo() + i); in visitSelect()
3859 DAG.getNode(OpCode, dl, VT, LHSVal.getValue(LHSVal.getResNo() + i)); in visitSelect()
3866 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i)); in visitSelect()
3867 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i)); in visitSelect()
3870 LHSVal.getNode()->getValueType(LHSVal.getResNo() + i), Ops, Flags); in visitSelect()
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H A DScheduleDAGFast.cpp218 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in CopyAndMoveSuccessors()
H A DLegalizeTypes.cpp92 if (U.getResNo() == i) in PerformExpensiveChecks()
H A DDAGCombiner.cpp3246 if (V.getResNo() != 1) in getAsCarry()
3370 N1.getResNo() == 0) in visitADDLikeCommutative()
3608 if (Carry1.getResNo() != 1 || Carry0.getResNo() != 1) in combineUADDO_CARRYDiamond()
3787 (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0 && in visitUADDO_CARRYLike()
4008 DivRem.getResNo() == 0 && DivRem.getOperand(0) == Sub0 && in foldRemainderIdiom()
4033 Shl0.getResNo() == 0 && Shl0.getOperand(0) == Sub0) { in foldRemainderIdiom()
4394 N0.getResNo() == 0 && N0.hasOneUse()) in visitSUB()
7509 N0.getOperand(0).getResNo() == 0) || in visitAND()
7510 (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) { in visitAND()
12280 if (N0.getOpcode() == ISD::USUBO && N0.getResNo() == 1 && in visitSELECT()
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H A DLegalizeVectorOps.cpp256 return SDValue(Result, Op.getResNo()); in TranslateLegalizeResults()
270 return Results[Op.getResNo()]; in RecursivelyLegalizeResults()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DDAGISelMatcherOpt.cpp52 CT->getResNo() == 0) // CheckChildType checks res #0 in ContractNodes()
110 CT->getResNo() == 0) { // CheckChildType checks res #0 in ContractNodes()
131 CT->getResNo() == 0) { // CheckChildType checks res #0 in ContractNodes()
163 CT->getResNo() == 0) { // CheckChildType checks res #0 in ContractNodes()
215 CT->getResNo() == 0) { // CheckChildType checks res #0 in ContractNodes()
526 CTM->getResNo() != 0 || in FactorScope()
H A DDAGISelMatcherEmitter.cpp654 if (cast<CheckTypeMatcher>(N)->getResNo() == 0) { in EmitMatcher()
670 OS << "OPC_CheckTypeRes, " << cast<CheckTypeMatcher>(N)->getResNo() << ", "; in EmitMatcher()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DDAGISelMatcher.cpp356 if (CT->getResNo() >= getOpcode().getNumResults()) in isContradictoryImpl()
359 MVT::SimpleValueType NodeType = getOpcode().getKnownType(CT->getResNo()); in isContradictoryImpl()
H A DDAGISelMatcher.h528 unsigned getResNo() const { return ResNo; } in getResNo() function
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h158 unsigned getResNo() const { return ResNo; }
256 (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
321 unsigned getResNo() const { return Val.getResNo(); }
910 if (U.getResNo() == Value) {
3375 return (Op.getResNo() == 1 &&
H A DSDPatternMatch.h118 return N.getResNo() == ResNo && P.match(Ctx, N); in match()
174 return P.match(Ctx, N) && N->hasNUsesOfValue(NumUses, N.getResNo()); in match()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp1619 if (Op0 != N->getOperand(1) || !Op0->hasNUsesOfValue(2, Op0.getResNo()) || in PostprocessISelDAG()
2628 if (N.getResNo() != 0) break; in matchAddressRecursively()
3347 if (Use.getResNo() != Flags.getResNo()) in onlyUsesZeroFlag()
3357 if (FlagUse.getResNo() != 1) in onlyUsesZeroFlag()
3384 if (Use.getResNo() != Flags.getResNo()) in hasNoSignFlagUses()
3394 if (FlagUse.getResNo() != 1) in hasNoSignFlagUses()
3441 if (Use.getResNo() != Flags.getResNo()) in hasNoCarryFlagUses()
3454 if (FlagUse.getResNo() != 1) in hasNoCarryFlagUses()
3498 if (StoredVal.getResNo() != 0) return false; in isFusableLoadOpStorePattern()
3873 Op.getNode()->hasNUsesOfValue(NUses, Op.getResNo()); in matchBitExtract()
H A DX86InstrFragments.td710 N->getOperand(0).getResNo() == 1);
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1913 if (Op.getResNo() != 0 || NeedOF || NeedCF) { in EmitTest()
2239 if (Op.getResNo() == 1 && in isM68kLogicalCmp()
2245 if (Op.getResNo() == 2 && Opc == M68kISD::UMUL) in isM68kLogicalCmp()
2464 Cond.getOperand(0).getResNo() == 1 && in LowerBRCOND()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3451 CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) && in getCmp()
3456 CmpOp0.getResNo() == CmpOp0->getNumValues() - 1 && in getCmp()
3834 return Res.getValue(Op.getResNo()); in lowerSTRICT_FSETCC()
7852 if (Use.getResNo() != 0) in isI128MovedToParts()
7887 if (Use.getResNo() != 0) in isF128MovedToParts()
7986 } else if (Use.getResNo() == 0) in combineLOAD()
7998 Ops.push_back((Op.getNode() == N && Op.getResNo() == 0) ? Extract0 : Op); in combineLOAD()
9290 if (Op.getResNo() == 1 && isIntrinsicWithCC(Op, Tmp0, Tmp1)) { in computeKnownBitsForTargetNode()
9295 if (Op.getResNo() != 0 || VT == MVT::Untyped) in computeKnownBitsForTargetNode()
9402 if (Op.getResNo() != 0) in ComputeNumSignBitsForTargetNode()
H A DSystemZISelDAGToDAG.cpp1319 if (StoredVal.getResNo() != 0) in isFusableLoadOpStorePattern()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp5203 if (Cond.getResNo() == 1 && in LowerSELECT()
5802 if (Cond.getResNo() == 1 && in LowerBRCOND()
5851 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) && in LowerBR_CC()
13808 VecRed.getResNo() != 0 || in PerformADDVecReduce()
15232 Op0.getResNo() == 0 && Op1.getResNo() == 1) in PerformVMOVDRRCombine()
15615 unsigned ResNo = Op0.getResNo(); in PerformExtractEltToVMOVRRD()
15625 V->getOperand(0).getResNo() == ResNo; in PerformExtractEltToVMOVRRD()
16258 if (Use.getResNo() != Addr.getResNo() || User->getNumOperands() != 2) in CombineBaseUpdate()
16282 if (Use.getResNo() != Base.getResNo() || User == Addr.getNode() || in CombineBaseUpdate()
16353 if (User->getOpcode() != ISD::ADD || Use.getResNo() != Addr.getResNo()) in PerformMVEVLDCombine()
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