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Searched refs:getRegState (Results 1 – 12 of 12) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZPostRewrite.cpp121 .addReg(Src1Reg, getRegState(Src1MO) & getRegState(Src2MO)); in selectSELRMux()
134 .addReg(Src1Reg, getRegState(Src1MO)); in selectSELRMux()
141 .addReg(Src2Reg, getRegState(Src2MO)); in selectSELRMux()
215 .addReg(MI.getOperand(2).getReg(), getRegState(MI.getOperand(2))); in expandCondMove()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp630 unsigned RSA = getRegState(AdrOp); in splitMemRef()
734 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg()); in splitCombine()
742 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
757 unsigned RS = getRegState(Op1); in splitExt()
791 unsigned RS = getRegState(Op1); in splitShift()
911 unsigned RS1 = getRegState(Op1); in splitAslOr()
912 unsigned RS2 = getRegState(Op2); in splitAslOr()
H A DHexagonExpandCondsets.cpp643 unsigned PredState = getRegState(PredOp) & ~RegState::Kill; in genCondTfrFor()
647 unsigned SrcState = getRegState(SrcOp); in genCondTfrFor()
701 unsigned S = getRegState(ST); in split()
891 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg()); in predicateAt()
H A DHexagonInstrInfo.cpp1183 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1200 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill) in expandPostRAPseudo()
1205 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1221 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1223 .addReg(SrcOp.getReg(), getRegState(SrcOp)) in expandPostRAPseudo()
1238 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill) in expandPostRAPseudo()
1243 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1376 unsigned PState = getRegState(Op1); in expandPostRAPseudo()
1409 unsigned PState = getRegState(Op1); in expandPostRAPseudo()
H A DHexagonConstPropagation.cpp3001 .addReg(R1.Reg, getRegState(Acc), R1.SubReg); in rewriteHexConstUses()
3031 .addReg(Src1.getReg(), getRegState(Src1), Src1.getSubReg()) in rewriteHexConstUses()
3032 .addReg(OpR2.getReg(), getRegState(OpR2), OpR2.getSubReg()) in rewriteHexConstUses()
3067 .addReg(SR.Reg, getRegState(SO), SR.SubReg); in rewriteHexConstUses()
3099 .addReg(SR.Reg, getRegState(SO), SR.SubReg); in rewriteHexConstUses()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DUnreachableBlockElim.cpp222 .addReg(InputReg, getRegState(Input), InputSub); in run()
H A DMachinePipeliner.cpp599 .addReg(RegOp.getReg(), getRegState(RegOp), in preprocessPhiNodes()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h577 inline unsigned getRegState(const MachineOperand &RegOp) { in getRegState() function
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp633 .addUse(SrcReg, getRegState(SrcMI->getOperand(1))) in visitINSviGPR()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMConstantIslandPass.cpp2029 getRegState(Cmp.MI->getOperand(0))) in optimizeThumb2Branches()
H A DARMExpandPseudoInsts.cpp2218 unsigned MO1Flags = getRegState(MI.getOperand(1)) & ~RegState::Kill; in ExpandMI()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp6233 unsigned MaskState = getRegState(MIB->getOperand(1)); in expandPostRAPseudo()