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Searched refs:getRegInfo (Results 1 – 25 of 422) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineFloatingPointPredicateUtils.cpp25 const MachineRegisterInfo &MRI = MF.getRegInfo(); in queryDenormalMode()
33 const MachineRegisterInfo &MRI = MF.getRegInfo(); in lookThroughFAbs()
40 const MachineRegisterInfo &MRI = MF.getRegInfo(); in matchConstantFloat()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineUniformityAnalysis.cpp35 const auto &MRI = F.getRegInfo(); in markDefsDivergent()
72 const auto &RegInfo = F.getRegInfo(); in pushUsers()
105 auto *Def = F.getRegInfo().getVRegDef(Reg); in usesValueFromCycle()
116 const auto &RegInfo = F.getRegInfo(); in propagateTemporalDivergence()
141 const auto &RegInfo = F.getRegInfo(); in isDivergentUse()
160 assert(F.getRegInfo().isSSA() && "Expected to be run on SSA form!"); in computeMachineUniformityInfo()
H A DMachineInstr.cpp85 MRI = &MF->getRegInfo(); in tryToGetTargetInfo()
159 MachineRegisterInfo *MachineInstr::getRegInfo() { in getRegInfo() function in MachineInstr
161 return &MBB->getParent()->getRegInfo(); in getRegInfo()
165 const MachineRegisterInfo *MachineInstr::getRegInfo() const { in getRegInfo() function in MachineInstr
167 return &MBB->getParent()->getRegInfo(); in getRegInfo()
239 MachineRegisterInfo *MRI = getRegInfo(); in addOperand()
307 MachineRegisterInfo *MRI = getRegInfo(); in removeOperand()
2527 auto *MRI = getRegInfo(); in changeDebugValuesDefReg()
2617 return std::tuple(getRegInfo()->getType(getOperand(0).getReg()), in getFirst2LLTs()
2618 getRegInfo()->getType(getOperand(1).getReg())); in getFirst2LLTs()
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H A DMachineSSAContext.cpp54 return F->getRegInfo().getVRegDef(value)->getParent(); in getDefBlock()
73 const MachineRegisterInfo &MRI = Phi.getMF()->getRegInfo(); in isConstantOrUndefValuePhi()
106 auto *MRI = &F->getRegInfo(); in print()
H A DSwiftErrorValueTracking.cpp37 auto VReg = MF->getRegInfo().createVirtualRegister(RC); in getOrCreateVReg()
59 Register VReg = MF->getRegInfo().createVirtualRegister(RC); in getOrCreateVRegDefAt()
133 Register VReg = MF->getRegInfo().createVirtualRegister(RC); in createEntriesInEntryBlock()
242 UpwardsUse ? UUseVReg : MF->getRegInfo().createVirtualRegister(RC); in propagateVRegs()
258 MachineRegisterInfo &MRI = MF->getRegInfo(); in propagateVRegs()
H A DMachineConvergenceVerifier.cpp40 const MachineRegisterInfo &MRI = Context.getFunction()->getRegInfo(); in checkConvergenceTokenProduced()
50 const MachineRegisterInfo &MRI = Context.getFunction()->getRegInfo(); in findAndCheckConvergenceTokenUsed()
H A DLivePhysRegs.cpp176 const MachineRegisterInfo &MRI = MF.getRegInfo(); in addCalleeSavedRegs()
251 const MachineRegisterInfo &MRI = MF.getRegInfo(); in computeLiveIns()
262 const MachineRegisterInfo &MRI = MF.getRegInfo(); in addLiveIns()
278 const MachineRegisterInfo &MRI = MF.getRegInfo(); in recomputeLivenessFlags()
H A DLiveIntervalCalc.cpp42 const MachineRegisterInfo *MRI = getRegInfo(); in calculate()
123 const MachineRegisterInfo *MRI = getRegInfo(); in createDeadDefs()
136 const MachineRegisterInfo *MRI = getRegInfo(); in extendToUses()
H A DRegAllocPBQP.cpp453 if (!MF.getRegInfo().isAllocatable(DstReg)) in apply()
566 const MachineRegisterInfo &MRI = MF.getRegInfo(); in findVRegIntervalsToAlloc()
580 const MCPhysReg *CSR = MF.getRegInfo().getCalleeSavedRegs(); in isACalleeSavedRegister()
592 const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo(); in initializeGraph()
755 MachineRegisterInfo &MRI = MF.getRegInfo(); in finalizeAlloc()
767 if (!VRM.getRegInfo().isReserved(CandidateReg)) { in finalizeAlloc()
813 MF.getRegInfo().freezeReservedRegs(); in runOnMachineFunction()
892 const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo(); in PrintNodeInfo()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFixBrTableDefaults.cpp62 auto ExtMI = MF.getRegInfo().getVRegDef(MI.getOperand(0).getReg()); in fixBrTableIndex()
68 if (MF.getRegInfo().use_nodbg_empty(ExtDefReg)) { in fixBrTableIndex()
75 MF.getRegInfo().createVirtualRegister(&WebAssembly::I32RegClass); in fixBrTableIndex()
127 MachineRegisterInfo &MRI = MF.getRegInfo(); in fixBrTableDefault()
H A DWebAssemblyRegNumbering.cpp63 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction()
83 unsigned NumVRegs = MF.getRegInfo().getNumVirtRegs(); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp58 MF.getRegInfo().createVirtualRegister(&getGlobalBaseRegClass(MF)); in getGlobalBaseReg()
76 MachineRegisterInfo &RegInfo = MF.getRegInfo(); in initGlobalBaseReg()
88 MF.getRegInfo().addLiveIn(Mips::T9_64); in initGlobalBaseReg()
116 MF.getRegInfo().addLiveIn(Mips::T9); in initGlobalBaseReg()
151 MF.getRegInfo().addLiveIn(Mips::V0); in initGlobalBaseReg()
H A DMipsRegisterBankInfo.cpp158 const MachineRegisterInfo &MRI = MF.getRegInfo(); in skipCopiesOutgoing()
172 const MachineRegisterInfo &MRI = MF.getRegInfo(); in skipCopiesIncoming()
185 const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo(); in AmbiguousRegDefUseContainer()
319 const MachineRegisterInfo &MRI = MF.getRegInfo(); in setTypesAccordingToPhysicalRegister()
385 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrMapping()
696 LegalizationArtifactCombiner ArtCombiner(Builder, MF->getRegInfo(), LegInfo); in applyMappingImpl()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCExpandPseudos.cpp65 Register AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandStore()
90 Register Ra = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTLZ()
91 Register Rb = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTLZ()
118 Register R = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTTZ()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchExpandPseudoInsts.cpp193 MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass); in expandPcalau12iInstPair()
269 MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass); in expandLargeAddressLoad()
272 ? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass) in expandLargeAddressLoad()
276 ? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass) in expandLargeAddressLoad()
280 ? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass) in expandLargeAddressLoad()
372 MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass); in expandLoadAddressTLSLE()
374 MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass); in expandLoadAddressTLSLE()
402 MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass); in expandLoadAddressTLSLE()
489 MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass); in expandLoadAddressTLSDesc()
511 MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass); in expandLoadAddressTLSDesc()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp210 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2) && in getCalleeSavedRegs()
561 const MachineRegisterInfo *MRI = &MF.getRegInfo(); in getRegAllocationHints()
762 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerDynamicAlloc()
851 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in prepareDynamicAlloca()
859 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in prepareDynamicAlloca()
868 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca()
876 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca()
972 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
984 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
1017 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXPeephole.cpp78 const auto &MRI = MF.getRegInfo(); in isCVTAToLocalCombinationCandidate()
106 const auto &MRI = MF.getRegInfo(); in CombineCVTAToLocal()
151 const auto &MRI = MF.getRegInfo(); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DSMEPeepholeOpt.cpp131 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); in optimizeStartStopPairs()
243 assert(MI.getMF()->getRegInfo().isSSA() && "Expected to be run on SSA form!"); in visitRegSequence()
245 MachineRegisterInfo &MRI = MI.getMF()->getRegInfo(); in visitRegSequence()
312 assert(MF.getRegInfo().isSSA() && "Expected to be run on SSA form!"); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRegPressure.h319 reset(MBB.getParent()->getRegInfo(), in reset()
325 reset(MI.getMF()->getRegInfo(), LIS.getInstructionIndex(MI).getDeadSlot()); in reset()
454 auto &MRI = (*R.begin())->getParent()->getParent()->getRegInfo(); in getLiveRegMap()
484 MI.getParent()->getParent()->getRegInfo()); in getLiveRegsAfter()
490 MI.getParent()->getParent()->getRegInfo()); in getLiveRegsBefore()
H A DSIFrameLowering.cpp91 ScratchSGPR = findUnusedRegister(MF.getRegInfo(), LiveUnits, RC); in getVGPRSpillLaneOrTempRegister()
196 MF->getRegInfo().addLiveIn(GitPtrLo); in buildGitPtr()
243 MachineRegisterInfo &MRI = MF.getRegInfo(); in saveToMemory()
293 MachineRegisterInfo &MRI = MF.getRegInfo(); in restoreFromMemory()
411 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitEntryFunctionFlatScratchInit()
462 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitEntryFunctionFlatScratchInit()
544 MachineRegisterInfo &MRI = MF.getRegInfo(); in getEntryFunctionReservedScratchRsrcReg()
614 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitEntryFunctionPrologue()
862 MF.getRegInfo().addLiveIn(MFI->getImplicitBufferPtrUserSGPR()); in emitEntryFunctionScratchRsrcRegSetup()
941 MachineRegisterInfo &MRI = MF.getRegInfo(); in buildScratchExecCopy()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVGlobalRegistry.cpp141 return createTypeVReg(MIRBuilder.getMF().getRegInfo()); in createTypeVReg()
302 Register Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy); in createConstFP()
303 CurMF->getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass); in createConstFP()
354 Register Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy); in createConstInt()
355 CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass); in createConstInt()
403 MachineRegisterInfo &MRI = MF.getRegInfo(); in buildConstantInt()
449 Res = MF.getRegInfo().createGenericVirtualRegister(LLTy); in buildConstantFP()
450 MF.getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass); in buildConstantFP()
500 Register Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy); in getOrCreateCompositeOrNull()
501 CurMF->getRegInfo().setRegClass(Res, getRegClass(SpvType)); in getOrCreateCompositeOrNull()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp114 auto &MRI = MF->getRegInfo(); in foldSimpleCrossClassCopies()
165 auto &MRI = MF->getRegInfo(); in foldCopyDup()
256 auto &MRI = MF.getRegInfo(); in optimizeNZCVDefs()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp424 RISCVOutgoingValueHandler Handler(MIRBuilder, MF.getRegInfo(), Ret); in lowerReturn()
472 MachineRegisterInfo &MRI = MF.getRegInfo(); in saveVarArgRegisters()
544 MachineRegisterInfo &MRI = MF.getRegInfo(); in lowerFormalArguments()
572 RISCVFormalArgHandler Handler(MIRBuilder, MF.getRegInfo()); in lowerFormalArguments()
634 RISCVOutgoingValueHandler ArgHandler(MIRBuilder, MF.getRegInfo(), Call); in lowerCall()
650 constrainOperandRegClass(MF, *TRI, MF.getRegInfo(), in lowerCall()
662 RISCVCallReturnHandler RetHandler(MIRBuilder, MF.getRegInfo(), Call); in lowerCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterBankInfo.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInsertReadWriteCSR.cpp117 MachineRegisterInfo *MRI = &MBB.getParent()->getRegInfo(); in INITIALIZE_PASS()
159 MachineRegisterInfo *MRI = &MBB.getParent()->getRegInfo(); in emitWriteRoundingMode()

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