Searched refs:getRegClasses (Results 1 – 7 of 7) sorted by relevance
187 for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) { in visitRegisterBankClasses()204 BitVector BV(RegisterClassHierarchy.getRegClasses().size()); in visitRegisterBankClasses()225 (RegisterClassHierarchy.getRegClasses().size() + 31) / 32); in emitBaseClassImplementation()253 << RegisterClassHierarchy.getRegClasses().size() << ");\n"; in emitBaseClassImplementation()322 for (const auto &Class : RegisterClassHierarchy.getRegClasses()) { in run()
137 const auto &RegisterClasses = Bank.getRegClasses(); in runEnums()210 unsigned NumRCs = RegBank.getRegClasses().size(); in EmitRegUnitPressure()217 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure()1000 const auto &RegisterClasses = RegBank.getRegClasses(); in runMCDesc()1161 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetHeader()1203 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetDesc()1831 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { in debugDump()1853 for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) { in debugDump()
32 for (const auto &RC : T.getRegBank().getRegClasses()) { in getRegisterValueType()
1258 auto &RegClassList = Target.getRegBank().getRegClasses(); in buildRegisterClasses()
120 auto &RegClasses = RegBank->getRegClasses(); in getRegNamespace()183 auto &RegClasses = RegBank.getRegClasses(); in getSuperRegForSubReg()244 for (const auto &RC : getRegBank().getRegClasses()) { in getRegisterVTs()258 for (const auto &RC : getRegBank().getRegClasses()) in ReadLegalValueTypes()
764 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; } in getRegClasses() function766 const std::list<CodeGenRegisterClass> &getRegClasses() const { in getRegClasses() function
1007 auto &RegClasses = RegBank.getRegClasses(); in computeSubClasses()1070 auto &RegClasses = RegBank.getRegClasses(); in getMatchingSubClassWithSubRegs()1736 for (auto &RegClass : RegBank.getRegClasses()) { in computeUberSets()2015 auto &RegClasses = getRegClasses(); in computeRegUnitSets()2459 for (const auto &RC : getRegClasses()) { in getRegClassForRegister()2500 for (const auto &RC : getRegClasses()) { in getMinimalPhysRegClass()