| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostSelectOptimize.cpp | 184 if (MRI.getRegClassOrNull(Dst) != GPRRegClass || in foldCopyDup()
185 MRI.getRegClassOrNull(Src) != FPRRegClass) in foldCopyDup()
201 if (MRI.getRegClassOrNull(UseOp0) == FPRRegClass && in foldCopyDup()
202 MRI.getRegClassOrNull(UseOp1) == GPRRegClass) in foldCopyDup()
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| H A D | AArch64RegisterBankInfo.cpp | 1031 auto Idx = MRI.getRegClassOrNull(Src) == &AArch64::XSeqPairsClassRegClass in getInstrMapping()
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| H A D | AArch64InstructionSelector.cpp | 4119 MRI.getRegClassOrNull(I.getOperand(1).getReg()); in selectUnmergeValues()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InstructionSelect.cpp | 178 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg); in runOnMachineFunction()
270 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg); in runOnMachineFunction()
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| H A D | Utils.cpp | 69 auto *OldRegClass = MRI.getRegClassOrNull(Reg); in constrainOperandRegClass()
95 } else if (OldRegClass != MRI.getRegClassOrNull(Reg)) { in constrainOperandRegClass()
217 return DstRBC.is<const RegisterBank *>() && MRI.getRegClassOrNull(SrcReg) && in canReplaceReg()
219 *MRI.getRegClassOrNull(SrcReg)); in canReplaceReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPreLegalizer.cpp | 116 auto *RC = MRI.getRegClassOrNull(MI->getOperand(0).getReg()); in addConstantsToTrack()
117 if (!MRI.getRegClassOrNull(Reg) && RC) in addConstantsToTrack()
289 if (!MRI.getRegClassOrNull(Reg)) in propagateSPIRVType()
381 if (auto *RC = MRI.getRegClassOrNull(Reg)) { in insertAssignInstr()
506 auto *RCReg = MRI.getRegClassOrNull(Reg); in generateAssignInstrs()
507 auto *RCPrimary = MRI.getRegClassOrNull(PrimaryReg); in generateAssignInstrs()
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| H A D | SPIRVInstrInfo.cpp | 63 auto DefRegClass = MRI.getRegClassOrNull(MI.getOperand(0).getReg()); in isTypeDeclInstr()
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| H A D | SPIRVBuiltins.cpp | 585 if (!MRI->getRegClassOrNull(ArgReg))
762 if (!MRI->getRegClassOrNull(Tmp)) in buildAtomicCompareExchangeInst()
1076 if (!MRI->getRegClassOrNull(ScopeReg)) in generateGroupInst()
1085 if (!MRI->getRegClassOrNull(ArgReg)) in generateGroupInst()
2007 if (!MRI->getRegClassOrNull(GWSPtr)) in buildNDRange()
2498 if (!MIRBuilder.getMRI()->getRegClassOrNull(ReturnRegister)) in lowerBuiltin()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MIRVRegNamerUtils.cpp | 171 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg); in createVirtualRegisterWithLowerName()
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| H A D | MIRCanonicalizerPass.cpp | 319 if (!MRI.getRegClassOrNull(Dst)) in propagateLocalCopies()
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| H A D | TargetRegisterInfo.cpp | 175 if (RegInfo.getRegClassOrNull(Reg)) in printRegClassOrBank()
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| H A D | MachineVerifier.cpp | 1171 const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(Dst); in verifyPreISelGenericInstruction()
1172 if (DstRC && DstRC != MRI->getRegClassOrNull(Src)) { in verifyPreISelGenericInstruction()
2527 const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg); in visitMachineOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUGlobalISelDivergenceLowering.cpp | 92 if (MRI->getRegClassOrNull(DstReg)) { in markAsLaneMask()
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| H A D | SIMachineFunctionInfo.cpp | 777 const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg); in usesAGPRs()
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| H A D | AMDGPUInstructionSelector.cpp | 178 if (!MRI->getRegClassOrNull(SrcReg)) in selectCOPY()
456 if (!MRI->getRegClassOrNull(Dst1Reg)) in selectG_UADDO_USUBO_UADDE_USUBE()
1549 if (!MRI->getRegClassOrNull(Reg)) in selectEndCfIntrinsic()
2142 if (!MRI->getRegClassOrNull(CCReg)) in selectG_SELECT()
2871 if (!MRI->getRegClassOrNull(CondReg)) in selectG_BRCOND()
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| H A D | AMDGPULegalizerInfo.cpp | 2886 if (!B.getMRI()->getRegClassOrNull(PCReg)) in buildPCRelGlobalAddress()
2904 Register AddrLo = !RequiresHighHalf && !MRI.getRegClassOrNull(DstReg) in buildAbsGlobalAddress()
2908 if (!MRI.getRegClassOrNull(AddrLo)) in buildAbsGlobalAddress()
2930 Register AddrDst = !MRI.getRegClassOrNull(DstReg) in buildAbsGlobalAddress()
2934 if (!MRI.getRegClassOrNull(AddrDst)) in buildAbsGlobalAddress()
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| H A D | SIISelLowering.cpp | 15722 const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg); in finalizeLowering()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineRegisterInfo.h | 232 const TargetRegisterClass *RC = getRegClassOrNull(VReg); in shouldTrackSubRegLiveness()
670 const TargetRegisterClass *getRegClassOrNull(Register Reg) const { in getRegClassOrNull() function
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 1238 const TargetRegisterClass *SrcRC = MRI->getRegClassOrNull(SrcReg); in simplifyCode()
1239 const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(DstReg); in simplifyCode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | MVETPAndVPTOptimisationsPass.cpp | 617 const TargetRegisterClass *RegClass = RegInfo.getRegClassOrNull(DstReg); in IsWritingToVCCR()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 342 const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg); in selectCopy()
1585 if (!MRI.getRegClassOrNull(DstReg)) { in selectImplicitDefOrPHI()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 4134 return MF ? MF->getRegInfo().getRegClassOrNull(Reg) : nullptr; in getRegClass()
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