| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRewritePartialRegUses.cpp | 233 << TRI->getRegClassName(SubRegRC) in getRegClassWithShiftedSubregs()
420 << ':' << TRI->getRegClassName(RC) << '\n'); in rewriteReg()
438 LLVM_DEBUG(dbgs() << TRI->getRegClassName(SubRegRC) << " & " in rewriteReg()
439 << TRI->getRegClassName(OpDescRC) << " = "); in rewriteReg()
448 LLVM_DEBUG(dbgs() << TRI->getRegClassName(SubRegRC) << '\n'); in rewriteReg()
459 << TRI->getRegClassName(RC) << " -> " in rewriteReg()
461 << TRI->getRegClassName(NewRC) << '\n'); in rewriteReg()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveStacks.cpp | 81 OS << " [" << TRI->getRegClassName(RC) << "]\n"; in print()
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| H A D | RegisterBank.cpp | 95 OS << LS << TRI->getRegClassName(&RC); in print()
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| H A D | RegAllocBase.cpp | 107 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg())) in allocatePhysRegs()
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| H A D | RegisterClassInfo.cpp | 189 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["; in compute()
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| H A D | VirtRegMap.cpp | 152 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; in print()
160 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; in print()
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| H A D | ExecutionDomainFix.cpp | 423 << TRI->getRegClassName(RC) << " **********\n"); in runOnMachineFunction()
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| H A D | LiveRangeEdit.cpp | 504 << TRI->getRegClassName(MRI.getRegClass(LI.reg())) << '\n'; in calculateRegClassAndHint()
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| H A D | MachineVerifier.cpp | 2515 << TRI->getRegClassName(DRC) << " register.\n"; in visitMachineOperand()
2600 << TRI->getRegClassName( in visitMachineOperand()
2613 errs() << "Register class " << TRI->getRegClassName(RC) in visitMachineOperand()
2619 errs() << "Register class " << TRI->getRegClassName(RC) in visitMachineOperand()
2642 errs() << "Expected a " << TRI->getRegClassName(DRC) in visitMachineOperand()
2643 << " register, but got a " << TRI->getRegClassName(RC) in visitMachineOperand()
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| H A D | RegisterScavenging.cpp | 276 TRI->getRegClassName(&RC) +
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| H A D | TargetRegisterInfo.cpp | 176 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower(); in printRegClassOrBank()
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| H A D | AggressiveAntiDepBreaker.cpp | 529 LLVM_DEBUG(dbgs() << " " << TRI->getRegClassName(RC)); in GetRenameRegisters()
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| H A D | RegAllocPBQP.cpp | 895 const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg)); in PrintNodeInfo()
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| H A D | InlineSpiller.cpp | 1294 << TRI.getRegClassName(MRI.getRegClass(edit.getReg())) in spill()
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| H A D | RegAllocFast.cpp | 898 << " in class " << TRI->getRegClassName(&RC) in allocVirtReg()
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| H A D | RegisterCoalescer.cpp | 2087 << TRI->getRegClassName(CP.getNewRC()) << " with "; in joinCopy()
4266 << TRI->getRegClassName(MRI->getRegClass(Reg)) << '\n'); in runOnMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 824 const char *getRegClassName(const TargetRegisterClass *Class) const { in getRegClassName() function
825 return MCRegisterInfo::getRegClassName(Class->MC); in getRegClassName()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.h | 122 const char* getRegClassName(unsigned RegClassID) const;
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| H A D | AMDGPUDisassembler.cpp | 1159 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { in getRegClassName() function in AMDGPUDisassembler
1161 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); in getRegClassName()
1184 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
1232 *CommentStream << "Warning: " << getRegClassName(SRegClassID) in createSRegOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 111 dbgs() << "Register class: " << getRegClassName(RC) << "\n"; in getCallerSavedRegs()
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| H A D | HexagonBitTracker.cpp | 108 << TRI.getRegClassName(&RC) << '\n'; in mask()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 456 const char *getRegClassName(const MCRegisterClass *Class) const { in getRegClassName() function
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIRParser.cpp | 711 TRI->getRegClassName(Info.D.RC) + "' for virtual register " + in setupRegisterInfo()
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| H A D | MIParser.cpp | 279 std::make_pair(StringRef(TRI->getRegClassName(RC)).lower(), RC)); in initNames2RegClasses()
1590 Twine(TRI.getRegClassName(RegInfo.D.RC))); in parseRegisterClassOrBank()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUInstPrinter.cpp | 814 O << "/*Invalid register, operand has \'" << MRI.getRegClassName(&RC) in printRegularOperand()
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