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Searched refs:getRegClassName (Results 1 – 25 of 32) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRewritePartialRegUses.cpp223 LLVM_DEBUG(dbgs() << TRI->getRegClassName(SubRegRC) in getRegClassWithShiftedSubregs()
403 << ':' << TRI->getRegClassName(RC) << '\n'); in rewriteReg()
413 << TRI->getRegClassName(RC) << " -> " in rewriteReg()
415 << TRI->getRegClassName(NewRC) << '\n'); in rewriteReg()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterBank.cpp95 OS << LS << TRI->getRegClassName(&RC); in print()
H A DLiveStacks.cpp107 OS << " [" << TRI->getRegClassName(RC) << "]\n"; in print()
H A DRegAllocBase.cpp109 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg())) in allocatePhysRegs()
H A DRegisterClassInfo.cpp197 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["; in compute()
H A DVirtRegMap.cpp153 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; in print()
161 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; in print()
H A DExecutionDomainFix.cpp423 << TRI->getRegClassName(RC) << " **********\n"); in runOnMachineFunction()
H A DLiveRangeEdit.cpp501 << TRI->getRegClassName(MRI.getRegClass(LI.reg())) << '\n'; in calculateRegClassAndHint()
H A DRegisterScavenging.cpp275 TRI->getRegClassName(&RC) + in spill()
H A DMachineVerifier.cpp2643 << TRI->getRegClassName(DRC) << " register.\n"; in visitMachineOperand()
2728 << TRI->getRegClassName(TII->getRegClass(MCID, MONum, TRI, *MF)) in visitMachineOperand()
2740 OS << "Register class " << TRI->getRegClassName(RC) in visitMachineOperand()
2747 OS << "Register class " << TRI->getRegClassName(RC) in visitMachineOperand()
2771 OS << "Expected a " << TRI->getRegClassName(DRC) in visitMachineOperand()
2772 << " register, but got a " << TRI->getRegClassName(RC) in visitMachineOperand()
H A DTargetRegisterInfo.cpp175 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower(); in printRegClassOrBank()
H A DAggressiveAntiDepBreaker.cpp533 LLVM_DEBUG(dbgs() << " " << TRI->getRegClassName(RC)); in GetRenameRegisters()
H A DRegAllocPBQP.cpp895 const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg)); in PrintNodeInfo()
H A DRegAllocFast.cpp917 << " in class " << TRI->getRegClassName(&RC) in allocVirtReg()
H A DInlineSpiller.cpp1318 << TRI.getRegClassName(MRI.getRegClass(edit.getReg())) in spill()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.h108 const char* getRegClassName(unsigned RegClassID) const;
H A DAMDGPUDisassembler.cpp1385 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { in getRegClassName() function in AMDGPUDisassembler
1387 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); in getRegClassName()
1410 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
1458 *CommentStream << "Warning: " << getRegClassName(SRegClassID) in createSRegOperand()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h871 const char *getRegClassName(const TargetRegisterClass *Class) const { in getRegClassName() function
872 return MCRegisterInfo::getRegClassName(Class->MC); in getRegClassName()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp106 dbgs() << "Register class: " << getRegClassName(RC) << "\n"; in getCallerSavedRegs()
H A DHexagonBitTracker.cpp99 << TRI.getRegClassName(&RC) << '\n'; in mask()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h472 const char *getRegClassName(const MCRegisterClass *Class) const { in getRegClassName() function
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp798 << TRI->getName(Reg) << " of class " << TRI->getRegClassName(RC) in getLoadStoreRegOpcode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
H A DMIRParser.cpp781 TRI->getRegClassName(Info.D.RC) + in setupRegisterInfo()
H A DMIParser.cpp287 std::make_pair(StringRef(TRI->getRegClassName(RC)).lower(), RC)); in initNames2RegClasses()
1598 Twine(TRI.getRegClassName(RegInfo.D.RC))); in parseRegisterClassOrBank()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp724 O << "/*Invalid register, operand has \'" << MRI.getRegClassName(&RC) in printRegularOperand()

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