Searched refs:getRegClassForTypeOnBank (Results 1 – 6 of 6) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 49 getRegClassForTypeOnBank(Register Reg, MachineRegisterInfo &MRI) const;
111 const TargetRegisterClass *RC = getRegClassForTypeOnBank(DstReg, MRI); in selectCopy()
120 const TargetRegisterClass *MipsInstructionSelector::getRegClassForTypeOnBank( in getRegClassForTypeOnBank() function in MipsInstructionSelector
427 DefRC = getRegClassForTypeOnBank(DestReg, MRI); in select()
575 MRI.setRegClass(Dst, getRegClassForTypeOnBank(Dst, MRI)); in select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVInstructionSelector.cpp | 58 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB) const;
699 DefRC = getRegClassForTypeOnBank(DefTy, RB); in select()
966 const TargetRegisterClass *RISCVInstructionSelector::getRegClassForTypeOnBank( in getRegClassForTypeOnBank() function in RISCVInstructionSelector
1013 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank( in selectCopy()
1036 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank( in selectImplicitDef()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 571 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB, in getRegClassForTypeOnBank() function
1001 RC = getRegClassForTypeOnBank(Ty, RB); in selectDebugInstr()
1968 getRegClassForTypeOnBank(Ty, RBI.getRegBank(AArch64::FPRRegBankID)); in selectVectorAshrLshr()
2607 DefRC = getRegClassForTypeOnBank(DefTy, RB); in select()
2781 const TargetRegisterClass &FPRRC = *getRegClassForTypeOnBank(DefTy, RB); in select()
3076 auto *RC = getRegClassForTypeOnBank(MemTy, RB); in select()
3092 auto *RC = getRegClassForTypeOnBank(MemTy, RB); in select()
3106 auto SubRegRC = getRegClassForTypeOnBank(MRI.getType(OldDst), RB); in select()
3296 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB); in select()
3300 const TargetRegisterClass *SrcRC = getRegClassForTypeOnBank(SrcTy, SrcRB); in select()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 372 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank) const { in getRegClassForTypeOnBank() function
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| H A D | AMDGPUInstructionSelector.cpp | 314 DefRC = TRI.getRegClassForTypeOnBank(DefTy, RB); in selectPHI()
330 TRI.getRegClassForTypeOnBank(SrcTy, *RB); in selectPHI()
2609 TRI.getRegClassForTypeOnBank(SrcTy, *SrcBank); in selectG_SZA_EXT()
3129 const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(Ty, *DstRB); in selectG_PTRMASK()
3130 const TargetRegisterClass *SrcRC = TRI.getRegClassForTypeOnBank(Ty, *SrcRB); in selectG_PTRMASK()
3132 TRI.getRegClassForTypeOnBank(MaskTy, *MaskRB); in selectG_PTRMASK()
3248 TRI.getRegClassForTypeOnBank(SrcTy, *SrcRB); in selectG_EXTRACT_VECTOR_ELT()
3250 TRI.getRegClassForTypeOnBank(DstTy, *DstRB); in selectG_EXTRACT_VECTOR_ELT()
3330 TRI.getRegClassForTypeOnBank(VecTy, *VecRB); in selectG_INSERT_VECTOR_ELT()
3332 TRI.getRegClassForTypeOnBank(ValTy, *ValRB); in selectG_INSERT_VECTOR_ELT()
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| H A D | SIRegisterInfo.cpp | 3883 return getRegClassForTypeOnBank(MRI.getType(MO.getReg()), *RB); in getConstrainedRegClassForOperand()
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