Searched refs:getRegClassForReg (Results 1 – 8 of 8) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNPreRAOptimizations.cpp | 276 TRI->getRegClassForReg(*MRI, Src) == &AMDGPU::VGPR_32RegClass) in run()
281 TRI->getRegClassForReg(*MRI, Dst) == &AMDGPU::VGPR_32RegClass) in run()
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| H A D | SIRegisterInfo.h | 319 const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI,
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| H A D | SILoadStoreOptimizer.cpp | 1182 return TRI->getRegClassForReg(*MRI, Dst->getReg()); in getDataRegClass()
1185 return TRI->getRegClassForReg(*MRI, Src->getReg()); in getDataRegClass()
1188 return TRI->getRegClassForReg(*MRI, Src->getReg()); in getDataRegClass()
1191 return TRI->getRegClassForReg(*MRI, Dst->getReg()); in getDataRegClass()
1194 return TRI->getRegClassForReg(*MRI, Src->getReg()); in getDataRegClass()
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| H A D | AMDGPUWaitSGPRHazards.cpp | 313 AMDGPU::getRegBitWidth(*TRI->getRegClassForReg(*MRI, Reg)) / 32; in runOnMachineBasicBlock()
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| H A D | SIRegisterInfo.cpp | 1590 const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg); in buildSpillLoadStore()
3698 SIRegisterInfo::getRegClassForReg(const MachineRegisterInfo &MRI, in getRegClassForReg() function in SIRegisterInfo
3706 const TargetRegisterClass *SrcRC = getRegClassForReg(MRI, MO.getReg()); in getRegClassForOperandReg()
3712 const TargetRegisterClass *RC = getRegClassForReg(MRI, Reg); in isVGPR()
3719 const TargetRegisterClass *RC = getRegClassForReg(MRI, Reg); in isAGPR()
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| H A D | SIFoldOperands.cpp | 1243 const TargetRegisterClass *DestRC = TRI->getRegClassForReg(*MRI, DestReg); in foldOperand()
1334 TRI->getCoveringSubRegIndexes(TRI->getRegClassForReg(*MRI, UseReg), M, in foldOperand()
1419 TRI->getRegClassForReg(*MRI, OpToFold.getReg()); in foldOperand()
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| H A D | SIInstrInfo.cpp | 4912 const TargetRegisterClass *RC = RI.getRegClassForReg(MRI, Reg); in verifyInstruction()
4969 if (!MO.isReg() || !RI.hasVGPRs(RI.getRegClassForReg(MRI, MO.getReg()))) { in verifyInstruction()
6325 if (RI.hasAGPRs(RI.getRegClassForReg(MRI, MO.getReg())) && in legalizeOperandsVOP3()
6331 if (!RI.isSGPRClass(RI.getRegClassForReg(MRI, MO.getReg()))) in legalizeOperandsVOP3()
6532 RI.getRegClassForReg(MRI, OpReg), OpSubReg); in legalizeGenericOperand()
7839 NewDstRC == RI.getRegClassForReg(MRI, Inst.getOperand(1).getReg())) { in moveToVALUImpl()
9361 IsNullOrVectorRegister = !RI.isSGPRClass(RI.getRegClassForReg(MRI, Reg)); in isBasicBlockPrologue()
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| H A D | SIISelLowering.cpp | 16289 auto *RC = TRI->getRegClassForReg(MRI, Op.getReg()); in AdjustInstrPostInstrSelection()
16325 auto *RC = TRI->getRegClassForReg(MRI, Src2->getReg()); in AdjustInstrPostInstrSelection()
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