Searched refs:getRegClassConstraint (Results 1 – 11 of 11) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineCopyPropagation.cpp | 644 UseI.getRegClassConstraint(UseIdx, TII, TRI)) in isBackwardPropagatableRegClassCopy()
665 UseI.getRegClassConstraint(UseIdx, TII, TRI)) in isForwardableRegClassCopy()
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| H A D | RegisterBankInfo.cpp | 118 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, TRI); in getRegBankFromConstraints()
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| H A D | MachineInstr.cpp | 972 MachineInstr::getRegClassConstraint(unsigned OpIdx, in getRegClassConstraint() function in MachineInstr
1041 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect()
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| H A D | SplitKit.cpp | 604 DefMI->getRegClassConstraint(DefOperandIdx, &TII, &TRI); in rematWillIncreaseRestriction()
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| H A D | TargetInstrInfo.cpp | 1323 const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI); in reassociateOps()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVVectorPeephole.cpp | 819 MO.getReg(), True.getRegClassConstraint(MO.getOperandNo(), TII, TRI)); in foldVMergeToMask()
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| H A D | RISCVISelLowering.cpp | 21717 const TargetRegisterClass *RC = MI.getRegClassConstraint(0, &TII, TRI); in emitVFROUND_NOEXCEPT_MASK()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 1609 getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64LoadStoreOptimizer.cpp | 1048 MI.getRegClassConstraint(OpIdx, TII, TRI)) in mergePairedInsns()
1070 MI.getRegClassConstraint(OpIdx, TII, TRI)) in mergePairedInsns()
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| H A D | AArch64InstrInfo.cpp | 1364 Instr.getRegClassConstraint(OpIdx, TII, TRI); in UpdateOperandRegClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 4820 const TargetRegisterClass *RC = MI.getRegClassConstraint(I, this, &RI); in verifyInstruction()
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