Searched refs:getRegClassConstraint (Results 1 – 9 of 9) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineCopyPropagation.cpp | 562 UseI.getRegClassConstraint(UseIdx, TII, TRI)) in isBackwardPropagatableRegClassCopy()
583 UseI.getRegClassConstraint(UseIdx, TII, TRI)) in isForwardableRegClassCopy()
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| H A D | RegisterBankInfo.cpp | 121 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, TRI); in getRegBankFromConstraints()
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| H A D | MachineInstr.cpp | 945 MachineInstr::getRegClassConstraint(unsigned OpIdx, in getRegClassConstraint() function in MachineInstr
1014 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect()
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| H A D | TargetInstrInfo.cpp | 1091 const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI); in reassociateOps()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64LoadStoreOptimizer.cpp | 913 MI.getRegClassConstraint(OpIdx, TII, TRI)) in mergePairedInsns()
935 MI.getRegClassConstraint(OpIdx, TII, TRI)) in mergePairedInsns()
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| H A D | AArch64InstrInfo.cpp | 1250 Instr.getRegClassConstraint(OpIdx, TII, TRI); in UpdateOperandRegClass()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 1600 getRegClassConstraint(unsigned OpIdx,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 4645 const TargetRegisterClass *RC = MI.getRegClassConstraint(I, this, &RI); in verifyInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 18572 const TargetRegisterClass *RC = MI.getRegClassConstraint(0, &TII, TRI); in emitVFROUND_NOEXCEPT_MASK()
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