| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsOptionRecord.h | 47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
49 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); in MipsRegInfoRecord()
50 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); in MipsRegInfoRecord()
51 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()
52 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); in MipsRegInfoRecord()
53 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID)); in MipsRegInfoRecord()
54 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); in MipsRegInfoRecord()
55 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID)); in MipsRegInfoRecord()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNPreRAOptimizations.cpp | 104 bool IsAGPRDst = TRI->isAGPRClass(MRI->getRegClass(Reg)); in processReg()
126 bool IsAGPRSrc = TRI->isAGPRClass(MRI->getRegClass(SrcReg)); in processReg()
255 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in run()
274 MRI->getRegClass(Dst) == &AMDGPU::VGPR_16RegClass && in run()
279 MRI->getRegClass(Src) == &AMDGPU::VGPR_16RegClass && in run()
285 if (MRI->getRegClass(Dst) == &AMDGPU::VGPR_32RegClass && in run()
286 MRI->getRegClass(Src) == &AMDGPU::VGPR_16RegClass) { in run()
290 if (MRI->getRegClass(Dst) == &AMDGPU::VGPR_16RegClass && in run()
291 MRI->getRegClass(Src) == &AMDGPU::VGPR_32RegClass) in run()
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| H A D | SIFixSGPRCopies.cpp | 210 ? MRI.getRegClass(SrcReg) in getCopyRegClasses()
217 ? MRI.getRegClass(DstReg) in getCopyRegClasses()
261 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
285 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
672 const TargetRegisterClass *SrcRC = MRI->getRegClass(MO.getReg()); in run()
835 const TargetRegisterClass *RC0 = MRI->getRegClass(PHIRes); in processPHINode()
872 MRI->getRegClass(MaybeVGPRConstMO.getReg()); in tryMoveVGPRConstToSGPR()
893 TRI->hasVectorRegisters(MRI->getRegClass(SrcReg))) { in lowerSpecialCase()
931 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in analyzeVGPRToSGPRCopy()
1091 assert(MRI->getRegClass(DstReg) == &AMDGPU::SReg_32RegClass || in lowerVGPR2SGPRCopies()
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| H A D | AMDGPURewriteAGPRCopyMFMA.cpp | 111 const TargetRegisterClass *VirtRegRC = MRI.getRegClass(VReg); in run()
177 MRI.getRegClass(Src2->getReg()); in run()
191 TII.getRegClass(TII.get(AGPROp), Src2->getOperandNo(), &TRI, MF); in run()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyPeephole.cpp | 67 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in maybeRewriteToDrop()
98 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough()
149 if (MRI.getRegClass(NewReg) != MRI.getRegClass(OldReg)) in runOnMachineFunction()
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| H A D | WebAssemblyExplicitLocals.cpp | 333 const TargetRegisterClass *RC = MRI.getRegClass(DefReg); in runOnMachineFunction()
366 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction()
438 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction()
474 typeForRegClass(MRI.getRegClass(Reg))); in runOnMachineFunction()
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| H A D | WebAssemblyMemIntrinsicResults.cpp | 170 if (MRI.getRegClass(FromReg) != MRI.getRegClass(ToReg)) in optimizeCall()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterBank.cpp | 26 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in RegisterBank()
37 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
92 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
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| H A D | PeepholeOptimizer.cpp | 794 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
805 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
891 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
919 RC = MRI->getRegClass(UseMI->getOperand(0).getReg()); in INITIALIZE_PASS_DEPENDENCY()
1069 const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg); in findNextSource()
1099 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in insertPHI()
1189 const TargetRegisterClass *DefRC = MRI->getRegClass(Dst.Reg); in optimizeCoalescableCopyImpl()
1276 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in rewriteSource()
1334 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in optimizeUncoalescableCopy()
1427 MRI->getRegClass(DstReg) == MRI->getRegClass(Reg)) { in foldImmediate()
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| H A D | InitUndef.cpp | 157 const TargetRegisterClass *TargetRegClass = MRI->getRegClass(Reg); in handleSubReg()
211 const TargetRegisterClass *TargetRegClass = MRI->getRegClass(MO.getReg()); in fixupIllOperand()
235 TII->getRegClass(MI.getDesc(), UseOpIdx, TRI, MF); in processBasicBlock()
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| H A D | DetectDeadLanes.cpp | 73 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in isCrossCopy()
170 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in transferUsedLanes()
289 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in determineInitialDefinedLanes()
354 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes()
454 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64MIPeepholeOpt.cpp | 259 MRI->getRegClass(SrcMI->getOperand(1).getReg()); in visitORR()
327 const TargetRegisterClass *RC = MRI->getRegClass(DstReg); in visitINSERT()
550 TII->getRegClass(TII->get(Opcode.first), 0, TRI, *MF); in splitTwoPartImm()
552 TII->getRegClass(TII->get(Opcode.first), 1, TRI, *MF); in splitTwoPartImm()
556 : TII->getRegClass(TII->get(Opcode.second), 0, TRI, *MF); in splitTwoPartImm()
560 : TII->getRegClass(TII->get(Opcode.second), 1, TRI, *MF); in splitTwoPartImm()
576 MRI->constrainRegClass(NewDstReg, MRI->getRegClass(DstReg)); in splitTwoPartImm()
620 if (MRI->getRegClass(SrcMI->getOperand(1).getReg()) == in visitINSviGPR()
648 const TargetRegisterClass *RC = MRI->getRegClass(MI->getOperand(0).getReg()); in is64bitDefwithZeroHigh64bit()
697 MRI->constrainRegClass(NewDef, MRI->getRegClass(OldDef)); in visitINSvi64lane()
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| H A D | SMEPeepholeOpt.cpp | 124 const TargetRegisterClass *RC = MRI.getRegClass(R); in isSVERegOp()
246 switch (MRI.getRegClass(MI.getOperand(0).getReg())->getID()) { in visitRegSequence()
281 MRI.getRegClass(CopySrcOp->getReg()); in visitRegSequence()
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| H A D | AArch64AdvSIMDScalarPass.cpp | 107 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
114 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
116 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterBankInfo.cpp | 147 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
159 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
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| H A D | A15SDOptimizer.cpp | 139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
271 MRI->getRegClass(MI->getOperand(1).getReg()); in optimizeSDPattern()
272 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
515 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || in optimizeAllLanesPattern()
516 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { in optimizeAllLanesPattern()
532 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { in optimizeAllLanesPattern()
538 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && in optimizeAllLanesPattern()
635 MRI->constrainRegClass(NewReg, MRI->getRegClass(Use->getReg())); in runOnInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXFMAMutate.cpp | 124 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != in processBlock()
125 MRI.getRegClass(AddendSrcReg)) in processBlock()
130 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) in processBlock()
230 MRI.getRegClass(OldFMAReg))) in processBlock()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | |
| H A D | X86TileConfig.cpp | 79 unsigned RegClassID = MRI->getRegClass(Reg)->getID(); in INITIALIZE_PASS_DEPENDENCY()
178 unsigned AMXRegNum = TRI->getRegClass(X86::TILERegClassID)->getNumRegs(); in runOnMachineFunction()
243 unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R)); in runOnMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 134 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
135 const TargetRegisterClass *getRegClass(LLT Ty, Register Reg,
176 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const { in getRegClass() function in X86InstructionSelector
215 X86InstructionSelector::getRegClass(LLT Ty, Register Reg, in getRegClass() function in X86InstructionSelector
218 return getRegClass(Ty, RegBank); in getRegClass()
267 RC = getRegClass(Ty, RB); in selectDebugInstr()
298 getRegClass(MRI.getType(SrcReg), SrcRegBank); in selectCopy()
328 getRegClass(MRI.getType(DstReg), DstRegBank); in selectCopy()
839 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectTruncOrPtrToInt()
840 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); in selectTruncOrPtrToInt()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | InlineAsm.h | 318 unsigned getRegClass() const { return Bitfield::get<RegClass>(Storage); } in getRegClass() function
380 if (!getRegClass()) in hasRegClassConstraint()
382 RC = getRegClass() - 1; in hasRegClassConstraint()
406 assert(getRegClass() == 0 && "Register class already set"); in setRegClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenPredicate.cpp | 115 const TargetRegisterClass *RC = MRI->getRegClass(R); in INITIALIZE_PASS_DEPENDENCY()
312 if (MRI->getRegClass(PR.Reg) != PredRC) in isScalarPred()
411 const TargetRegisterClass *RC = MRI->getRegClass(OutR.Reg); in convertToPredForm()
455 if (MRI->getRegClass(DR.Reg) != PredRC) in eliminatePredCopies()
457 if (MRI->getRegClass(SR.Reg) != PredRC) in eliminatePredCopies()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.cpp | 865 if (MRI.getRegClass(AArch64::GPR32RegClassID).contains(Rm)) in printRangePrefetchAlias()
867 &MRI.getRegClass(AArch64::GPR64RegClassID)); in printRangePrefetchAlias()
1672 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) || in printVectorList()
1673 MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) || in printVectorList()
1674 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg) || in printVectorList()
1675 MRI.getRegClass(AArch64::PPR2RegClassID).contains(Reg) || in printVectorList()
1676 MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg)) in printVectorList()
1678 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) || in printVectorList()
1679 MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) || in printVectorList()
1680 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg)) in printVectorList()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVVMV0Elimination.cpp | 163 MRI.getRegClass(MO.getReg()) == &RISCV::VMV0RegClass) { in runOnMachineFunction()
165 assert((MRI.getRegClass(MO.getReg()) != &RISCV::VMV0RegClass || in runOnMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 133 TII->getRegClass(II, i + II.getNumDefs(), TRI, *MF)); in EmitCopyFromReg()
158 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg()
205 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); in CreateVirtualRegisters()
234 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); in CreateVirtualRegisters()
338 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); in AddRegisterOperand()
412 II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF)) in AddOperand()
475 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg()
541 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode()
598 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) in EmitSubregNode()
637 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); in EmitCopyToRegClassNode()
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