Searched refs:getRegBitWidth (Results 1 – 11 of 11) sorted by relevance
94 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub)); in mask()271 assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch"); in evaluate()311 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0; in evaluate()369 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()703 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()758 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32); in evaluate()770 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32); in evaluate()832 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()864 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()969 uint16_t RW = getRegBitWidth(PD); in evaluate()[all …]
329 uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const { in getRegBitWidth() function in BT::MachineEvaluator350 uint16_t BW = getRegBitWidth(RR); in getCell()709 uint16_t W = getRegBitWidth(Reg); in mask()733 uint16_t W = getRegBitWidth(RD); in evaluate()747 uint16_t WD = getRegBitWidth(RD); in evaluate()748 uint16_t WS = getRegBitWidth(RS); in evaluate()805 uint16_t DefBW = ME.getRegBitWidth(DefRR); in visitPHI()882 uint16_t DefBW = ME.getRegBitWidth(RD); in visitNonBranch()
1854 unsigned getRegBitWidth(unsigned Reg) const;1991 unsigned W = getRegBitWidth(DefR.Reg); in evaluate() 2152 unsigned BW = getRegBitWidth(R1.Reg); in evaluate() 2359 unsigned HexagonConstEvaluator::getRegBitWidth(unsigned Reg) const { in getRegBitWidth() function in HexagonConstEvaluator 2697 unsigned W = getRegBitWidth(DefR.Reg); in evaluateHexCondMove() 2751 unsigned BW = getRegBitWidth(DefR.Reg); in evaluateHexExt() 2899 unsigned W = getRegBitWidth(R); in rewriteHexConstDefs()
397 uint16_t getRegBitWidth(const RegisterRef &RR) const;
1345 unsigned getRegBitWidth(unsigned RCID);1348 unsigned getRegBitWidth(const MCRegisterClass &RC);
2401 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth() function2540 unsigned getRegBitWidth(const MCRegisterClass &RC) { in getRegBitWidth() function2541 return getRegBitWidth(RC.getID()); in getRegBitWidth()2548 return getRegBitWidth(RCID) / 8; in getRegOperandSize()
1352 const unsigned RegWidth = AMDGPU::getRegBitWidth(*RC) / 8; in buildSpillLoadStore()2607 unsigned AMDGPU::getRegBitWidth(const TargetRegisterClass &RC) { in getRegBitWidth() function in AMDGPU2608 return getRegBitWidth(RC.getID()); in getRegBitWidth()2986 const unsigned RegBitWidth = AMDGPU::getRegBitWidth(*RC); in getRegSplitParts()
836 if (AMDGPU::getRegBitWidth(VDataRCID) > 64 && in createsVALUHazard()848 AMDGPU::getRegBitWidth(Desc.operands()[SRsrcIdx].RegClass) == 256); in createsVALUHazard()854 if (AMDGPU::getRegBitWidth(Desc.operands()[DataIdx].RegClass) > 64) in createsVALUHazard()
1083 if (UseOp->getSubReg() && AMDGPU::getRegBitWidth(*FoldRC) == 64) { in foldOperand()1086 if (AMDGPU::getRegBitWidth(*UseRC) != 64) in foldOperand()
3234 int NumInsts = AMDGPU::getRegBitWidth(*RC) / 32; in canInsertSelect()3249 int NumInsts = AMDGPU::getRegBitWidth(*RC) / 32; in canInsertSelect()
896 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); in printRegularOperand()