Searched refs:getRegBitWidth (Results 1 – 13 of 13) sorted by relevance
84 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub)); in mask()263 assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch"); in evaluate()303 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0; in evaluate()361 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()695 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()750 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32); in evaluate()762 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32); in evaluate()824 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()856 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()961 uint16_t RW = getRegBitWidth(PD); in evaluate()[all …]
324 uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const { in getRegBitWidth() function in BT::MachineEvaluator345 uint16_t BW = getRegBitWidth(RR); in getCell()704 uint16_t W = getRegBitWidth(Reg); in mask()728 uint16_t W = getRegBitWidth(RD); in evaluate()742 uint16_t WD = getRegBitWidth(RD); in evaluate()743 uint16_t WS = getRegBitWidth(RS); in evaluate()800 uint16_t DefBW = ME.getRegBitWidth(DefRR); in visitPHI()877 uint16_t DefBW = ME.getRegBitWidth(RD); in visitNonBranch()
1851 unsigned getRegBitWidth(unsigned Reg) const;1988 unsigned W = getRegBitWidth(DefR.Reg); in evaluate()2149 unsigned BW = getRegBitWidth(R1.Reg); in evaluate()2357 unsigned HexagonConstEvaluator::getRegBitWidth(unsigned Reg) const { in getRegBitWidth() function in HexagonConstEvaluator2701 unsigned W = getRegBitWidth(DefR.Reg); in evaluateHexCondMove()2755 unsigned BW = getRegBitWidth(DefR.Reg); in evaluateHexExt()2903 unsigned W = getRegBitWidth(R); in rewriteHexConstDefs()
394 uint16_t getRegBitWidth(const RegisterRef &RR) const;
504 unsigned getRegBitWidth(const TargetRegisterClass &RC);
313 AMDGPU::getRegBitWidth(*TRI->getRegClassForReg(*MRI, Reg)) / 32; in runOnMachineBasicBlock()
819 if (AMDGPU::getRegBitWidth(VDataRCID) > 64 && in createsVALUHazard()831 AMDGPU::getRegBitWidth(Desc.operands()[SRsrcIdx].RegClass) == 256); in createsVALUHazard()840 if (AMDGPU::getRegBitWidth(VDataRCID) > 64) in createsVALUHazard()
1593 const unsigned RegWidth = AMDGPU::getRegBitWidth(*RC) / 8; in buildSpillLoadStore()3331 unsigned AMDGPU::getRegBitWidth(const TargetRegisterClass &RC) { in getRegBitWidth() function in AMDGPU3332 return getRegBitWidth(RC.getID()); in getRegBitWidth()3684 const unsigned RegBitWidth = AMDGPU::getRegBitWidth(*RC); in getRegSplitParts()
3295 int NumInsts = AMDGPU::getRegBitWidth(*RC) / 32; in canInsertSelect()3310 int NumInsts = AMDGPU::getRegBitWidth(*RC) / 32; in canInsertSelect()
164 if (AMDGPU::getRegBitWidth(SrcRC->getID()) == 16) { in selectCOPY()
1576 unsigned getRegBitWidth(unsigned RCID);1579 unsigned getRegBitWidth(const MCRegisterClass &RC);
2650 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth() function2793 unsigned getRegBitWidth(const MCRegisterClass &RC) { in getRegBitWidth() function2794 return getRegBitWidth(RC.getID()); in getRegBitWidth()2801 return getRegBitWidth(RCID) / 8; in getRegOperandSize()
795 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); in printRegularOperand()