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Searched refs:getRegBank (Results 1 – 25 of 46) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenTarget.cpp157 CodeGenRegBank &CodeGenTarget::getRegBank() const { in getRegBank() function in CodeGenTarget
166 return getRegBank().getRegistersByName().lookup(Name); in getRegisterByName()
171 return *getRegBank().getRegClass(R); in getRegisterClass()
176 const CodeGenRegister *Reg = getRegBank().getReg(R); in getRegisterVTs()
178 for (const auto &RC : getRegBank().getRegClasses()) { in getRegisterVTs()
192 for (const auto &RC : getRegBank().getRegClasses()) in ReadLegalValueTypes()
H A DCodeGenTarget.h123 CodeGenRegBank &getRegBank() const;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.cpp57 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
62 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
67 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
246 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
378 MRI.setRegBank(Ext.getReg(0), getRegBank(AArch64::GPRRegBankID)); in applyMappingImpl()
398 MRI.setRegBank(ConstReg, getRegBank(AArch64::GPRRegBankID)); in applyMappingImpl()
526 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
723 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
724 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
803 (getRegBank(ScalarReg, MRI, TRI) == &AArch64::FPRRegBank || in getInstrMapping()
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H A DAArch64InstructionSelector.cpp801 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp()
960 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in getRegClassesForCopy()
961 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in getRegClassesForCopy()
1019 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
1020 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
1186 assert(RBI.getRegBank(False, MRI, TRI)->getID() == in emitSelect()
1187 RBI.getRegBank(True, MRI, TRI)->getID() && in emitSelect()
1196 if (RBI.getRegBank(True, MRI, TRI)->getID() != AArch64::GPRRegBankID) { in emitSelect()
1675 assert(RBI.getRegBank(CompareReg, MRI, TRI)->getID() == in emitCBZ()
1968 getRegClassForTypeOnBank(Ty, RBI.getRegBank(AArch64::FPRRegBankID)); in selectVectorAshrLshr()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegBankLegalize.cpp114 SgprRB(&RBI.getRegBank(AMDGPU::SGPRRegBankID)), in AMDGPURegBankLegalizeCombiner()
115 VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)), in AMDGPURegBankLegalizeCombiner()
116 VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {}; in AMDGPURegBankLegalizeCombiner()
177 assert(MRI.getRegBank(RALSrc) == VgprRB); in tryCombineCopy()
328 assert(MRI.getRegBank(Dst)->getID() == AMDGPU::SGPRRegBankID); in runOnMachineFunction()
H A DAMDGPURegBankSelect.cpp94 SgprRB(&RBI.getRegBank(AMDGPU::SGPRRegBankID)), in RegBankSelectHelper()
95 VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)), in RegBankSelectHelper()
96 VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {} in RegBankSelectHelper()
H A DAMDGPUGlobalISelUtils.cpp127 const RegisterBank *VgprRB = &RBI.getRegBank(AMDGPU::VGPRRegBankID); in unmergeReadAnyLane()
137 const RegisterBank *SgprRB = &RBI.getRegBank(AMDGPU::SGPRRegBankID); in buildReadAnyLane()
H A DAMDGPURegBankLegalizeHelper.cpp37 SgprRB(&RBI.getRegBank(AMDGPU::SGPRRegBankID)), in RegBankLegalizeHelper()
38 VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)), in RegBankLegalizeHelper()
39 VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {} in RegBankLegalizeHelper()
413 const RegisterBank *RB = MRI.getRegBank(MI.getOperand(0).getReg()); in lower()
726 [[maybe_unused]] const RegisterBank *RB = MRI.getRegBank(Reg); in applyMappingDst()
845 const RegisterBank *RB = MRI.getRegBank(Reg); in applyMappingSrc()
1043 const RegisterBank *RB = MRI.getRegBank(MI.getOperand(0).getReg()); in applyMappingTrivial()
1056 if (MRI.getRegBank(Reg) != RB) { in applyMappingTrivial()
H A DAMDGPUInstructionSelector.cpp392 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_AND_OR_XOR()
419 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_ADD_SUB()
615 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_EXTRACT()
647 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_MERGE_VALUES()
689 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_UNMERGE_VALUES()
742 const RegisterBank *DstBank = RBI.getRegBank(Dst, *MRI, TRI); in selectG_BUILD_VECTOR()
909 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_INSERT()
915 const RegisterBank *Src0Bank = RBI.getRegBank(Src0Reg, *MRI, TRI); in selectG_INSERT()
916 const RegisterBank *Src1Bank = RBI.getRegBank(Src1Reg, *MRI, TRI); in selectG_INSERT()
949 assert(RBI.getRegBank(DstReg, *MRI, TRI)->getID() == AMDGPU::VGPRRegBankID && in selectG_SBFX_UBFX()
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H A DAMDGPURegBankCombiner.cpp129 return RBI.getRegBank(Reg, MRI, TRI)->getID() == AMDGPU::VGPRRegBankID; in isVgprRegBank()
145 MRI.setRegBank(VgprReg, RBI.getRegBank(AMDGPU::VGPRRegBankID)); in getAsVgpr()
381 auto &RB = *MRI.getRegBank(AmtReg); in applyCanonicalizeZextShiftAmt()
H A DAMDGPURegisterBankInfo.cpp131 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, MRI, *RBI.TRI); in applyBank()
158 const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI); in applyBank()
212 assert(&getRegBank(AMDGPU::SGPRRegBankID) == &AMDGPU::SGPRRegBank && in AMDGPURegisterBankInfo()
213 &getRegBank(AMDGPU::VGPRRegBankID) == &AMDGPU::VGPRRegBank && in AMDGPURegisterBankInfo()
214 &getRegBank(AMDGPU::AGPRRegBankID) == &AMDGPU::AGPRRegBank); in AMDGPURegisterBankInfo()
668 const RegisterBank *Bank = getRegBank(Reg, *MRI, *TRI); in split64BitValueForMapping()
707 const RegisterBank *Bank = getRegBank(Src, MRI, *TRI); in buildReadFirstLane()
882 const RegisterBank *OpBank = getRegBank(OpReg, MRI, *TRI); in executeInWaterfallLoop()
991 const RegisterBank *OpBank = getRegBank(Reg, MRI, *TRI); in collectWaterfallOperands()
1019 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); in constrainOpWithReadfirstlane()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterBankInfo.h440 const RegisterBank &getRegBank(unsigned ID) { in getRegBank() function
585 const RegisterBank &getRegBank(unsigned ID) const { in getRegBank() function
586 return const_cast<RegisterBankInfo *>(this)->getRegBank(ID); in getRegBank()
599 const RegisterBank *getRegBank(Register Reg, const MachineRegisterInfo &MRI,
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
245 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
250 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
255 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
277 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
282 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
287 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectUnmergeValues()
520 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { in validReg()
930 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
931 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86RegisterBankInfo.cpp35 const RegisterBank &RBGPR = getRegBank(X86::GPRRegBankID); in X86RegisterBankInfo()
87 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
88 if (RB == &getRegBank(X86::PSRRegBankID)) in hasFPConstraints()
90 if (RB == &getRegBank(X86::GPRRegBankID)) in hasFPConstraints()
H A DX86InstructionSelector.cpp217 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
285 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
289 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
639 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp()
754 if (RBI.getRegBank(DefReg, MRI, TRI)->getID() != X86::GPRRegBankID) in selectConstant()
830 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectTruncOrPtrToInt()
831 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectTruncOrPtrToInt()
959 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectAnyext()
960 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectAnyext()
1082 auto *LhsBank = RBI.getRegBank(LhsReg, MRI, TRI); in selectFCmp()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterBankInfo.cpp
H A DX86InstructionSelector.cpp
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DDAGISelMatcherGen.cpp30 const CodeGenRegister *Reg = T.getRegBank().getReg(R); in getRegisterValueType()
32 for (const auto &RC : T.getRegBank().getRegClasses()) { in getRegisterValueType()
675 const CodeGenRegister *Reg = CGP.getTargetInfo().getRegBank().getReg(Def); in EmitResultLeafAsOperand()
724 const CodeGenRegBank &RB = CGP.getTargetInfo().getRegBank(); in EmitResultLeafAsOperand()
887 CGP.getTargetInfo().getRegBank().getReg(PhysRegInput.first); in EmitResultInstructionAsOperand()
H A DRegisterBankEmitter.cpp222 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank(); in emitBaseClassImplementation()
387 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank(); in run()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCRegisterBankInfo.cpp44 return getRegBank(PPC::FPRRegBankID); in getRegBankFromRegClass()
254 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterBankInfo.cpp73 const RegisterBank &RegBank = getRegBank(Idx); in verify()
84 RegisterBankInfo::getRegBank(Register Reg, const MachineRegisterInfo &MRI, in getRegBank() function in RegisterBankInfo
195 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
241 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp858 MRI->setRegBank(PtrToInt.getReg(0), RBI.getRegBank(RISCV::GPRBRegBankID)); in replacePtrWithInt()
1000 return RBI.getRegBank(Reg, *MRI, TRI)->getID() == RISCV::GPRBRegBankID; in isRegInGprb()
1004 return RBI.getRegBank(Reg, *MRI, TRI)->getID() == RISCV::FPRBRegBankID; in isRegInFprb()
1014 MRI->getType(DstReg), *RBI.getRegBank(DstReg, *MRI, TRI)); in selectCopy()
1037 MRI->getType(DstReg), *RBI.getRegBank(DstReg, *MRI, TRI)); in selectImplicitDef()
1221 if (RBI.getRegBank(DstReg, *MRI, TRI)->getID() == RISCV::FPRBRegBankID) { in selectSelect()
H A DRISCVRegisterBankInfo.cpp145 return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) == &RISCV::FPRBRegBank; in hasFPConstraints()
424 if (getRegBank(VReg, MRI, TRI) == &RISCV::FPRBRegBank || in getInstrMapping()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterBankInfo.cpp324 RBI.getRegBank(CopyInst->getOperand(Op).getReg(), MRI, TRI); in setTypesAccordingToPhysicalRegister()
660 MRI.setRegBank(Dest, getRegBank(Mips::GPRBRegBankID)); in setRegBank()
665 MRI.setRegBank(Dest, getRegBank(Mips::GPRBRegBankID)); in setRegBank()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/MIRParser/
H A DMIParser.h150 const RegisterBank *getRegBank(StringRef Name);

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