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Searched refs:getRegBank (Results 1 – 25 of 41) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86RegisterBankInfo.cpp35 const RegisterBank &RBGPR = getRegBank(X86::GPRRegBankID); in X86RegisterBankInfo()
57 return getRegBank(X86::GPRRegBankID); in getRegBankFromRegClass()
64 return getRegBank(X86::VECRRegBankID); in getRegBankFromRegClass()
69 return getRegBank(X86::PSRRegBankID); in getRegBankFromRegClass()
114 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
115 if (RB == &getRegBank(X86::PSRRegBankID)) in hasFPConstraints()
117 if (RB == &getRegBank(X86::GPRRegBankID)) in hasFPConstraints()
H A DX86InstructionSelector.cpp213 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
281 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
285 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
570 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp()
726 if (RBI.getRegBank(DefReg, MRI, TRI)->getID() != X86::GPRRegBankID) in selectConstant()
802 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectTruncOrPtrToInt()
803 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectTruncOrPtrToInt()
931 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectAnyext()
932 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectAnyext()
1069 *getRegClass(LLT::scalar(8), *RBI.getRegBank(ResultReg, MRI, TRI)), MRI); in selectFCmp()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.cpp57 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
62 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
67 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
263 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
289 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
291 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
423 MRI.setRegBank(Ext.getReg(0), getRegBank(AArch64::GPRRegBankID)); in applyMappingImpl()
536 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
712 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
713 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
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H A DAArch64InstructionSelector.cpp794 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp()
953 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in getRegClassesForCopy()
954 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in getRegClassesForCopy()
1011 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
1012 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
1178 assert(RBI.getRegBank(False, MRI, TRI)->getID() == in emitSelect()
1179 RBI.getRegBank(True, MRI, TRI)->getID() && in emitSelect()
1188 if (RBI.getRegBank(True, MRI, TRI)->getID() != AArch64::GPRRegBankID) { in emitSelect()
1667 assert(RBI.getRegBank(CompareReg, MRI, TRI)->getID() == in emitCBZ()
1960 getRegClassForTypeOnBank(Ty, RBI.getRegBank(AArch64::FPRRegBankID)); in selectVectorAshrLshr()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCRegisterBankInfo.cpp43 return getRegBank(PPC::GPRRegBankID); in getRegBankFromRegClass()
52 return getRegBank(PPC::FPRRegBankID); in getRegBankFromRegClass()
60 return getRegBank(PPC::VECRegBankID); in getRegBankFromRegClass()
63 return getRegBank(PPC::CRRegBankID); in getRegBankFromRegClass()
273 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
H A DPPCInstructionSelector.cpp138 const RegisterBank *DstRegBank = RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
245 const RegisterBank *DstRegBank = RBI.getRegBank(DstReg, MRI, TRI); in selectZExt()
741 I.getOpcode(), RBI.getRegBank(LdSt.getReg(0), MRI, TRI)->getID(), in select()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenTarget.cpp173 CodeGenRegBank &CodeGenTarget::getRegBank() const { in getRegBank() function in CodeGenTarget
234 return getRegBank().getRegistersByName().lookup(Name); in getRegisterByName()
238 return *getRegBank().getRegClass(R); in getRegisterClass()
242 const CodeGenRegister *Reg = getRegBank().getReg(R); in getRegisterVTs()
244 for (const auto &RC : getRegBank().getRegClasses()) { in getRegisterVTs()
258 for (const auto &RC : getRegBank().getRegClasses()) in ReadLegalValueTypes()
H A DCodeGenTarget.h122 CodeGenRegBank &getRegBank() const;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
245 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
250 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
255 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
277 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
282 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
287 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectUnmergeValues()
520 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { in validReg()
930 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
931 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
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H A DARMRegisterBankInfo.cpp142 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo()
196 return getRegBank(ARM::GPRRegBankID); in getRegBankFromRegClass()
203 return getRegBank(ARM::FPRRegBankID); in getRegBankFromRegClass()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterBankInfo.h440 const RegisterBank &getRegBank(unsigned ID) { in getRegBank() function
585 const RegisterBank &getRegBank(unsigned ID) const { in getRegBank() function
586 return const_cast<RegisterBankInfo *>(this)->getRegBank(ID); in getRegBank()
599 const RegisterBank *getRegBank(Register Reg, const MachineRegisterInfo &MRI,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVRegisterBankInfo.cpp136 return getRegBank(RISCV::GPRBRegBankID); in getRegBankFromRegClass()
142 return getRegBank(RISCV::FPRBRegBankID); in getRegBankFromRegClass()
156 return getRegBank(RISCV::VRBRegBankID); in getRegBankFromRegClass()
190 return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) == &RISCV::FPRBRegBank; in hasFPConstraints()
446 if (getRegBank(VReg, MRI, TRI) == &RISCV::FPRBRegBank || in getInstrMapping()
H A DRISCVInstructionSelector.cpp764 MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(RISCV::GPRBRegBankID)); in replacePtrWithInt()
881 return RBI.getRegBank(Reg, MRI, TRI)->getID() == RISCV::GPRBRegBankID; in isRegInGprb()
886 return RBI.getRegBank(Reg, MRI, TRI)->getID() == RISCV::FPRBRegBankID; in isRegInFprb()
897 MRI.getType(DstReg), *RBI.getRegBank(DstReg, MRI, TRI)); in selectCopy()
920 MRI.getType(DstReg), *RBI.getRegBank(DstReg, MRI, TRI)); in selectImplicitDef()
1132 if (RBI.getRegBank(DstReg, MRI, TRI)->getID() == RISCV::FPRBRegBankID) { in selectSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterBankInfo.cpp
H A DX86InstructionSelector.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterBankInfo.cpp92 return getRegBank(Mips::GPRBRegBankID); in getRegBankFromRegClass()
101 return getRegBank(Mips::FPRBRegBankID); in getRegBankFromRegClass()
353 RBI.getRegBank(CopyInst->getOperand(Op).getReg(), MRI, TRI); in setTypesAccordingToPhysicalRegister()
689 MRI.setRegBank(Dest, getRegBank(Mips::GPRBRegBankID)); in setRegBank()
694 MRI.setRegBank(Dest, getRegBank(Mips::GPRBRegBankID)); in setRegBank()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp294 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_AND_OR_XOR()
321 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_ADD_SUB()
517 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_EXTRACT()
549 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_MERGE_VALUES()
591 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_UNMERGE_VALUES()
644 const RegisterBank *DstBank = RBI.getRegBank(Dst, *MRI, TRI); in selectG_BUILD_VECTOR()
811 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_INSERT()
817 const RegisterBank *Src0Bank = RBI.getRegBank(Src0Reg, *MRI, TRI); in selectG_INSERT()
818 const RegisterBank *Src1Bank = RBI.getRegBank(Src1Reg, *MRI, TRI); in selectG_INSERT()
851 assert(RBI.getRegBank(DstReg, *MRI, TRI)->getID() == AMDGPU::VGPRRegBankID && in selectG_SBFX_UBFX()
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H A DAMDGPURegisterBankInfo.cpp131 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, MRI, *RBI.TRI); in applyBank()
158 const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI); in applyBank()
212 assert(&getRegBank(AMDGPU::SGPRRegBankID) == &AMDGPU::SGPRRegBank && in AMDGPURegisterBankInfo()
213 &getRegBank(AMDGPU::VGPRRegBankID) == &AMDGPU::VGPRRegBank && in AMDGPURegisterBankInfo()
214 &getRegBank(AMDGPU::AGPRRegBankID) == &AMDGPU::AGPRRegBank); in AMDGPURegisterBankInfo()
668 const RegisterBank *Bank = getRegBank(Reg, *MRI, *TRI); in split64BitValueForMapping()
707 const RegisterBank *Bank = getRegBank(Src, MRI, *TRI); in buildReadFirstLane()
882 const RegisterBank *OpBank = getRegBank(OpReg, MRI, *TRI); in executeInWaterfallLoop()
991 const RegisterBank *OpBank = getRegBank(Reg, MRI, *TRI); in collectWaterfallOperands()
1019 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); in constrainOpWithReadfirstlane()
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H A DAMDGPURegBankCombiner.cpp129 return RBI.getRegBank(Reg, MRI, TRI)->getID() == AMDGPU::VGPRRegBankID; in isVgprRegBank()
145 MRI.setRegBank(VgprReg, RBI.getRegBank(AMDGPU::VGPRRegBankID)); in getAsVgpr()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/
H A DM68kRegisterBankInfo.cpp64 return getRegBank(M68k::GPRRegBankID); in getRegBankFromRegClass()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DDAGISelMatcherGen.cpp30 const CodeGenRegister *Reg = T.getRegBank().getReg(R); in getRegisterValueType()
32 for (const auto &RC : T.getRegBank().getRegClasses()) { in getRegisterValueType()
678 const CodeGenRegister *Reg = CGP.getTargetInfo().getRegBank().getReg(Def); in EmitResultLeafAsOperand()
724 const CodeGenRegBank &RB = CGP.getTargetInfo().getRegBank(); in EmitResultLeafAsOperand()
886 CGP.getTargetInfo().getRegBank().getReg(PhysRegInputs[i].first); in EmitResultInstructionAsOperand()
H A DRegisterBankEmitter.cpp218 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank(); in emitBaseClassImplementation()
296 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank(); in run()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterBankInfo.cpp73 const RegisterBank &RegBank = getRegBank(Idx); in verify()
84 RegisterBankInfo::getRegBank(Register Reg, const MachineRegisterInfo &MRI, in getRegBank() function in RegisterBankInfo
198 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
243 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/MIRParser/
H A DMIParser.h151 const RegisterBank *getRegBank(StringRef Name); in PerTargetMIParsingState()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DRegBankSelect.cpp120 const RegisterBank *CurRegBank = RBI->getRegBank(Reg, *MRI, *TRI); in assignmentMatch()
244 const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI); in getRepairCost()
645 RBI->getRegBank(MI.getOperand(1).getReg(), *MRI, *TRI); in assignInstr()

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