| /freebsd/contrib/llvm-project/llvm/tools/llvm-tapi-diff/ |
| H A D | DiffEngine.h | |
| H A D | DiffEngine.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.cpp | 762 unsigned DVOrder = DV->getOrder(); in ProcessSDDbgValues()
984 return LHS->getOrder() < RHS->getOrder(); in EmitSchedule()
997 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order) in EmitSchedule()
1023 assert((*DI)->getOrder() >= LastOrder && in EmitSchedule()
1045 (*DLI)->getOrder() >= LastOrder && (*DLI)->getOrder() < Order; in EmitSchedule()
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| H A D | SDNodeDbgValue.h | 219 unsigned getOrder() const { return Order; } in getOrder() function
259 unsigned getOrder() const { return Order; } in getOrder() function
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| H A D | SelectionDAGDumper.cpp | 944 OS << " DbgVal(Order=" << getOrder() << ')'; in print()
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| /freebsd/stand/ficl/ |
| H A D | search.c | 109 static void getOrder(FICL_VM *pVM) in getOrder() function
370 dictAppendWord(dp, "get-order", getOrder, FW_DEFAULT); in ficlCompileSearch()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.cpp | 34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create()
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| H A D | AllocationOrder.h | 111 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder() function
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| H A D | RegAllocBase.cpp | 126 ArrayRef<MCPhysReg> AllocOrder = RegClassInfo.getOrder(RC); in allocatePhysRegs()
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| H A D | RegAllocFast.cpp | 938 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtReg()
993 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtRegUndef()
1072 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in defineVirtReg()
1163 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in useVirtReg()
1346 unsigned ClassSize0 = RegClassInfo.getOrder(&RC0).size(); in findAndSortDefOperandIndexes()
1347 unsigned ClassSize1 = RegClassInfo.getOrder(&RC1).size(); in findAndSortDefOperandIndexes()
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| H A D | BreakFalseDeps.cpp | 156 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
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| H A D | CriticalAntiDepBreaker.cpp | 399 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister()
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| H A D | AggressiveAntiDepBreaker.cpp | 609 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
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| H A D | RegAllocGreedy.cpp | 534 unsigned OrderLimit = Order.getOrder().size(); in getOrderLimit()
548 if (RegCosts[Order.getOrder().back()] >= CostPerUseLimit) { in getOrderLimit()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 101 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder() function
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterInfoEmitter.cpp | 1009 ArrayRef<Record *> Order = RC.getOrder(); in runMCDesc()
1045 ArrayRef<Record *> Order = RC.getOrder(); in runMCDesc()
1054 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() in runMCDesc()
1211 ArrayRef<Record *> Order = RC.getOrder(); in runTargetDesc()
1376 ArrayRef<Record *> Elems = RC.getOrder(oi); in runTargetDesc()
1389 if (RC.getOrder(oi).empty()) in runTargetDesc()
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| H A D | AsmMatcherEmitter.cpp | 1268 RegisterSet(RC.getOrder().begin(), RC.getOrder().end())); in buildRegisterClasses()
1342 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(), in buildRegisterClasses()
1343 RC.getOrder().end())]; in buildRegisterClasses()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreAllocateWWMRegs.cpp | 105 for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { in processDef()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Passes/ |
| H A D | StandardInstrumentations.h | 349 std::vector<std::string> &getOrder() { return Order; } in getOrder() function
350 const std::vector<std::string> &getOrder() const { return Order; } in getOrder() function
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| /freebsd/contrib/llvm-project/llvm/lib/Passes/ |
| H A D | StandardInstrumentations.cpp | 595 std::vector<std::string>::const_iterator BI = Before.getOrder().begin(); in report()
596 std::vector<std::string>::const_iterator BE = Before.getOrder().end(); in report()
597 std::vector<std::string>::const_iterator AI = After.getOrder().begin(); in report()
598 std::vector<std::string>::const_iterator AE = After.getOrder().end(); in report()
736 FD.getOrder().emplace_back(BBName); in generateFunctionData()
739 Data.getOrder().emplace_back(F.getName()); in generateFunctionData()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64A57FPLoadBalancing.cpp | 518 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.h | 455 ArrayRef<Record *> getOrder(unsigned No = 0) const { return Orders[No]; }
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 138 const SmallVectorImpl<MachineBasicBlock*> &getOrder() const { in getOrder() function in __anona50655620111::PostOrderLoopTraversal
1795 const SmallVectorImpl<MachineBasicBlock*> &PostOrder = DFS.getOrder(); in Expand()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Frontend/OpenMP/ |
| H A D | OMPIRBuilder.h | 253 unsigned getOrder() const { return Order; } in getOrder() function
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| /freebsd/contrib/llvm-project/llvm/lib/Frontend/OpenMP/ |
| H A D | OMPIRBuilder.cpp | 8449 GetMDInt(E.getOrder())}; in createOffloadEntriesAndInfoMetadata()
8452 OrderedEntries[E.getOrder()] = std::make_pair(&E, EntryInfo); in createOffloadEntriesAndInfoMetadata()
8473 GetMDInt(E.getFlags()), GetMDInt(E.getOrder())}; in createOffloadEntriesAndInfoMetadata()
8477 OrderedEntries[E.getOrder()] = std::make_pair(&E, varInfo); in createOffloadEntriesAndInfoMetadata()
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