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Searched refs:getOpRegClass (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h1147 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
1173 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8; in getOpSize()
H A DSIInstrInfo.cpp404 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16; in getMemOperandsWithOffsetWidth()
408 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8; in getMemOperandsWithOffsetWidth()
2338 const TargetRegisterClass *EltRC = getOpRegClass(MI, 2); in expandPostRAPseudo()
4895 const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx); in verifyInstruction()
5613 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI, in getOpRegClass() function in SIInstrInfo
6604 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) { in legalizeOperands()
6607 if (getOpRegClass(MI, 0) == &AMDGPU::VReg_1RegClass) { in legalizeOperands()
6610 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
6614 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
6644 const TargetRegisterClass *DstRC = getOpRegClass(MI, 0); in legalizeOperands()
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H A DSIFixSGPRCopies.cpp656 if (TRI->isSGPRClass(TII->getOpRegClass(MI, 0))) { in runOnMachineFunction()
H A DSIRegisterInfo.cpp2445 bool IsSALU = isSGPRClass(TII->getOpRegClass(*MI, FIOperandNum)); in eliminateFrameIndex()
H A DSIISelLowering.cpp15167 TRI.getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; in AddMemOpInit()
15171 InitIdx = TRI.getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; in AddMemOpInit()
15190 NewDst = MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in AddMemOpInit()