Home
last modified time | relevance | path

Searched refs:getOpRegClass (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp413 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16; in getMemOperandsWithOffsetWidth()
417 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8; in getMemOperandsWithOffsetWidth()
2344 const TargetRegisterClass *EltRC = getOpRegClass(MI, 2); in expandPostRAPseudo()
5080 const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx); in verifyInstruction()
5860 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI, in getOpRegClass() function in SIInstrInfo
6912 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) { in legalizeOperands()
6915 if (getOpRegClass(MI, 0) == &AMDGPU::VReg_1RegClass) { in legalizeOperands()
6918 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
6922 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
6952 const TargetRegisterClass *DstRC = getOpRegClass(MI, 0); in legalizeOperands()
[all …]
H A DSIInstrInfo.h1208 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
1234 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8; in getOpSize()
H A DSIFixSGPRCopies.cpp668 if (TRI->isSGPRClass(TII->getOpRegClass(MI, 0))) { in run()
H A DSIRegisterInfo.cpp3082 bool IsSALU = isSGPRClass(TII->getOpRegClass(*MI, FIOperandNum)); in eliminateFrameIndex()
H A DSIISelLowering.cpp16211 TRI.getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; in AddMemOpInit()
16215 InitIdx = TRI.getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; in AddMemOpInit()
16234 NewDst = MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in AddMemOpInit()