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Searched refs:getNumDefs (Results 1 – 25 of 81) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp98 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i) in init()
135 for (unsigned i = 0; i < MCID.getNumDefs(); ++i) { in init()
188 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i) in init()
530 unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs(); in checkRegistersReadOnly()
547 for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(), in registerUsed()
567 for (unsigned J = 0, N = Desc.getNumDefs(); J < N; ++J) in registerProducer()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DExecutionDomainFix.cpp239 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); in processDefs()
259 for (unsigned i = mi->getDesc().getNumDefs(), in visitHardInstr()
271 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { in visitHardInstr()
290 for (unsigned i = mi->getDesc().getNumDefs(), in visitSoftInstr()
H A DBreakFalseDeps.cpp195 for (unsigned i = MCID.getNumDefs(), e = MCID.getNumOperands(); i != e; ++i) { in processDefs()
217 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); in processDefs()
H A DPeepholeOptimizer.cpp230 NumDefs = MI.getDesc().getNumDefs(); in UncoalescableRewriter()
1237 assert(MI.getDesc().getNumDefs() == 1 && in optimizeCoalescableCopy()
1366 if (MCID.getNumDefs() != 1) in isLoadFoldable()
1385 if (MCID.getNumDefs() != 1 || !MI.getOperand(0).isReg()) in isMoveImmediate()
1571 if (MI.getDesc().getNumDefs() != 1) in findTargetRecurrence()
1842 for (unsigned i = MIDesc.getNumDefs(); i != MI->getNumOperands(); ++i) { in run()
1920 if (Def->getDesc().getNumDefs() != 1) in getNextSourceFromBitcast()
2133 (DefIdx < Def->getDesc().getNumDefs() || in getNextSourceImpl()
H A DDetectDeadLanes.cpp197 if (MI.getDesc().getNumDefs() != 1) in transferDefinedLanesStep()
345 assert(UseMI.getDesc().getNumDefs() == 1); in determineInitialUsedLanes()
H A DImplicitNullChecks.cpp368 if (MI.getDesc().getNumDefs() > 1) in isSuitableMemoryOp()
709 unsigned NumDefs = MI->getDesc().getNumDefs(); in insertFaultingInstr()
H A DInitUndef.cpp231 if (MI.getNumDefs() != 0 && MI.isRegTiedToUseOperand(0, &UseOpIdx)) { in processBasicBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPostLegalizer.cpp81 for (unsigned i = 0; i < I.getNumDefs(); ++i) { in processNewInstrs()
90 } else if (mayBeInserted(Opcode) && I.getNumDefs() == 1 && in processNewInstrs()
H A DSPIRVInstrInfo.cpp77 if (MI.getNumDefs() >= 1 && MI.getOperand(0).isReg()) { in isTypeDeclInstr()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp2000 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
2002 if (II.getNumDefs() >= 1) in fastEmitInst_r()
2022 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
2023 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
2025 if (II.getNumDefs() >= 1) in fastEmitInst_rr()
2046 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
2047 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
2048 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
2050 if (II.getNumDefs() >= 1) in fastEmitInst_rrr()
2073 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
[all …]
H A DScheduleDAGSDNodes.cpp132 if (ResNo >= II.getNumDefs() && II.hasImplicitDefOfPhysReg(Reg)) in CheckForPhysRegDependency()
473 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs()) in AddSchedEdges()
574 unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs(); in InitNodeNumDefs()
661 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs(); in computeOperandLatency()
H A DScheduleDAGRRList.cpp1283 NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
1428 for (unsigned i = 0; i < MCID.getNumDefs(); ++i) in DelayForLiveRegsBottomUp()
2124 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in MayReduceRegPressure()
2170 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in RegPressureDiff()
2308 unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs(); in unscheduledNode()
2325 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in unscheduledNode()
2839 unsigned NumRes = MCID.getNumDefs(); in canClobber()
2896 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in canClobberPhysRegDefs()
3079 unsigned NumRes = MCID.getNumDefs(); in AddPseudoTwoAddrDeps()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchDeadRegisterDefinitions.cpp75 for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) { in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVDeadRegisterDefinitions.cpp77 for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) { in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/MCA/
H A DInstrBuilder.cpp242 unsigned NumExplicitDefs = MCDesc.getNumDefs(); in verifyOperands()
317 unsigned NumExplicitDefs = MCDesc.getNumDefs(); in populateWrites()
446 unsigned NumExplicitUses = MCDesc.getNumOperands() - MCDesc.getNumDefs(); in populateReads()
455 for (unsigned I = 0, OpIndex = MCDesc.getNumDefs(); I < NumExplicitUses; in populateReads()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyInstPrinter.cpp323 else if (OpNo >= Desc.getNumDefs() && !IsVariadicDef) in printOperand()
330 if (OpNo < MII.get(MI->getOpcode()).getNumDefs() || IsVariadicDef) in printOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/MCTargetDesc/
H A DSPIRVMCCodeEmitter.cpp65 if (MCDesc.getNumDefs() == 1 && MCDesc.getNumOperands() >= 2) { in hasType()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.h264 return Desc.getNumDefs() < Desc.getNumOperands() && in isFirstDefTiedToFirstUse()
265 Desc.getOperandConstraint(Desc.getNumDefs(), MCOI::TIED_TO) == 0; in isFirstDefTiedToFirstUse()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64DeadRegisterDefinitionsPass.cpp143 for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) { in processMachineBasicBlock()
H A DAArch64FastISel.cpp1141 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx)); in addLoadStoreOperands()
1143 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1323 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1324 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1368 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1409 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1410 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1453 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1454 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rx()
2133 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs()); in emitStore()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLocalizer.cpp91 assert(MI.getDesc().getNumDefs() == 1 && in localizeInterBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLatencyMutations.cpp464 if (OI < MID.getNumDefs()) in markDPProducersConsumers()
470 if (OI < MID.getNumDefs()) in markDPProducersConsumers()
476 if (OI < MID.getNumDefs()) in markDPProducersConsumers()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrDesc.h249 unsigned getNumDefs() const { return NumDefs; } in getNumDefs() function
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h897 unsigned NumDefs = MI.getNumDefs(); in tryCombineUnmergeDefs()
1039 unsigned NumElts = Unmerge->getNumDefs(); in tryCombineMergeLike()
1045 if ((!UnmergeI) || (UnmergeI->getNumDefs() != NumElts) || in tryCombineMergeLike()
1068 unsigned NumDefs = MI.getNumDefs(); in tryCombineUnmergeValues()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DStackMaps.h175 NumDefs = MI->getNumDefs(); in StatepointOpers()

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