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Searched refs:getNamedOperand (Results 1 – 25 of 32) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPeepholeSDWA.cpp365 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) { in getSrcMods()
366 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) { in getSrcMods()
369 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) { in getSrcMods()
370 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers)) { in getSrcMods()
453 MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA()
454 MachineOperand *SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src0_sel); in convertToSDWA()
456 TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers); in convertToSDWA()
460 Src = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in convertToSDWA()
461 SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel); in convertToSDWA()
462 SrcMods = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers); in convertToSDWA()
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H A DGCNDPPCombine.cpp131 if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in isShrinkable()
229 auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask); in createDPPInst()
231 auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask); in createDPPInst()
248 if (auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst)) { in createDPPInst()
252 if (auto *SDst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::sdst)) { in createDPPInst()
266 TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg()), in createDPPInst()
284 auto *Mod0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0_modifiers); in createDPPInst()
296 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); in createDPPInst()
308 auto *Mod1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1_modifiers); in createDPPInst()
320 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst()
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H A DSILoadStoreOptimizer.cpp339 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm(); in getOpcodeWidth()
834 DMask = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); in setMI()
843 Format = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::format)->getImm(); in setMI()
850 CPol = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::cpol)->getImm(); in setMI()
963 const auto *TFEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::tfe); in dmasksCanBeCombined()
964 const auto *LWEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::lwe); in dmasksCanBeCombined()
1181 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) { in getDataRegClass()
1184 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::vdata)) { in getDataRegClass()
1187 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0)) { in getDataRegClass()
1190 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in getDataRegClass()
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H A DSILateBranchLowering.cpp158 *TII->getNamedOperand(MI, AMDGPU::OpName::numvgprs)); in expandChainCall()
162 .addDef(TII->getNamedOperand(MI, AMDGPU::OpName::src0)->getReg()); in expandChainCall()
164 *TII->getNamedOperand(MI, AMDGPU::OpName::src0)); in expandChainCall()
166 *TII->getNamedOperand(MI, AMDGPU::OpName::fbcallee)); in expandChainCall()
174 *TII->getNamedOperand(MI, AMDGPU::OpName::exec)); in expandChainCall()
176 *TII->getNamedOperand(MI, AMDGPU::OpName::fbexec)); in expandChainCall()
180 *TII->getNamedOperand(MI, AMDGPU::OpName::exec)); in expandChainCall()
H A DGCNVOPDUtils.cpp91 const MachineOperand &Src0 = *TII.getNamedOperand(MI, AMDGPU::OpName::src0); in checkVOPDRegConstraints()
115 const MachineOperand *Src = TII.getNamedOperand(MI, OpName); in checkVOPDRegConstraints()
141 const MachineOperand *Mods = TII.getNamedOperand(MI, OpName); in checkVOPDRegConstraints()
168 *TII.getNamedOperand(SecondMI, AMDGPU::OpName::src2); in checkVOPDRegConstraints()
174 *TII.getNamedOperand(FirstMI, AMDGPU::OpName::src2); in checkVOPDRegConstraints()
H A DGCNHazardRecognizer.cpp164 const MachineOperand *RegOp = TII->getNamedOperand(RegInstr, in getHWReg()
816 TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in createsVALUHazard()
896 if (auto *DstSel = TII->getNamedOperand(MI, AMDGPU::OpName::dst_sel)) in getDstSelForwardingOperand()
898 return TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in getDstSelForwardingOperand()
906 return TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in getDstSelForwardingOperand()
912 return TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in getDstSelForwardingOperand()
918 return TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in getDstSelForwardingOperand()
958 Register Def = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)->getReg(); in checkVALUHazards()
1041 MachineOperand *Src = TII.getNamedOperand(*VALU, AMDGPU::OpName::src0); in checkVALUHazards()
1143 TII->getNamedOperand(*RWLane, AMDGPU::OpName::src1); in checkRWLaneHazards()
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H A DSIOptimizeExecMasking.cpp602 MachineOperand *Src0 = TII->getNamedOperand(VCmp, AMDGPU::OpName::src0); in optimizeVCMPSaveExecSequence()
603 MachineOperand *Src1 = TII->getNamedOperand(VCmp, AMDGPU::OpName::src1); in optimizeVCMPSaveExecSequence()
623 if (auto *Mod = TII->getNamedOperand(VCmp, OperandName)) in optimizeVCMPSaveExecSequence()
674 MachineOperand *SaveExecSrc0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in tryRecordVCmpxAndSaveexecSequence()
698 MachineOperand *VCmpDest = TII->getNamedOperand(*VCmp, AMDGPU::OpName::sdst); in tryRecordVCmpxAndSaveexecSequence()
702 MachineOperand *Src0 = TII->getNamedOperand(*VCmp, AMDGPU::OpName::src0); in tryRecordVCmpxAndSaveexecSequence()
707 MachineOperand *Src1 = TII->getNamedOperand(*VCmp, AMDGPU::OpName::src1); in tryRecordVCmpxAndSaveexecSequence()
H A DSIOptimizeExecMaskingPreRA.cpp162 MachineOperand *Op1 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src0); in optimizeVcndVcmpPair()
163 MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1); in optimizeVcndVcmpPair()
181 Op1 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src0); in optimizeVcndVcmpPair()
182 Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1); in optimizeVcndVcmpPair()
183 MachineOperand *CC = TII->getNamedOperand(*Sel, AMDGPU::OpName::src2); in optimizeVcndVcmpPair()
H A DSIInstrInfo.cpp154 const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::sdst); in resultDependsOnExec()
375 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr); in getMemOperandsWithOffsetWidth()
376 OffsetOp = getNamedOperand(LdSt, AMDGPU::OpName::offset); in getMemOperandsWithOffsetWidth()
399 getNamedOperand(LdSt, AMDGPU::OpName::offset0); in getMemOperandsWithOffsetWidth()
401 getNamedOperand(LdSt, AMDGPU::OpName::offset1); in getMemOperandsWithOffsetWidth()
441 const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc); in getMemOperandsWithOffsetWidth()
445 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr); in getMemOperandsWithOffsetWidth()
449 getNamedOperand(LdSt, AMDGPU::OpName::offset); in getMemOperandsWithOffsetWidth()
452 getNamedOperand(LdSt, AMDGPU::OpName::soffset); in getMemOperandsWithOffsetWidth()
480 BaseOps.push_back(getNamedOperand(LdSt, AMDGPU::OpName::vaddr)); in getMemOperandsWithOffsetWidth()
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H A DSIInsertWaitcnts.cpp932 if (const auto *AddrOp = TII->getNamedOperand(Inst, AMDGPU::OpName::addr)) in updateByEvent()
937 TII->getNamedOperand(Inst, AMDGPU::OpName::data0)) in updateByEvent()
940 TII->getNamedOperand(Inst, AMDGPU::OpName::data1)) in updateByEvent()
954 *TII->getNamedOperand(Inst, AMDGPU::OpName::data), in updateByEvent()
958 *TII->getNamedOperand(Inst, AMDGPU::OpName::data), in updateByEvent()
967 *TII->getNamedOperand(Inst, AMDGPU::OpName::data), in updateByEvent()
980 *TII->getNamedOperand(Inst, AMDGPU::OpName::data), in updateByEvent()
986 *TII->getNamedOperand(Inst, AMDGPU::OpName::vdst), in updateByEvent()
1388 TII->getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); in applyPreexistingWaitcnt()
1540 TII->getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); in applyPreexistingWaitcnt()
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H A DAMDGPUMacroFusion.cpp46 const MachineOperand *Src2 = TII.getNamedOperand(SecondMI, in shouldScheduleAdjacent()
H A DSIShrinkInstructions.cpp428 MachineOperand &Src0 = *TII->getNamedOperand(MI, AMDGPU::OpName::src0); in shrinkMadFma()
429 MachineOperand &Src1 = *TII->getNamedOperand(MI, AMDGPU::OpName::src1); in shrinkMadFma()
430 MachineOperand &Src2 = *TII->getNamedOperand(MI, AMDGPU::OpName::src2); in shrinkMadFma()
831 MachineOperand *Op = TII->getNamedOperand(MI, AMDGPU::OpName::sdst); in tryReplaceDeadSDST()
1028 TII->getNamedOperand(MI, AMDGPU::OpName::src2); in run()
1041 const MachineOperand *SDst = TII->getNamedOperand(MI, in run()
1055 const MachineOperand *Src2 = TII->getNamedOperand(MI, in run()
H A DSIFoldOperands.cpp1200 if (TII->getNamedOperand(*UseMI, AMDGPU::OpName::srsrc)->getReg() != in foldOperand()
1207 *TII->getNamedOperand(*UseMI, AMDGPU::OpName::soffset); in foldOperand()
1660 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in tryFoldCndMask()
1661 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in tryFoldCndMask()
2064 if (!TII->getNamedOperand(MI, AMDGPU::OpName::clamp)->getImm()) in isClamp()
2068 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isClamp()
2069 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isClamp()
2081 = TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers)->getImm(); in isClamp()
2083 = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers)->getImm(); in isClamp()
2119 MachineOperand *DefClamp = TII->getNamedOperand(*Def, AMDGPU::OpName::clamp); in tryFoldClamp()
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H A DSIRegisterInfo.cpp1109 TII->getNamedOperand(MI, IsFlat ? AMDGPU::OpName::saddr in resolveFrameIndex()
1112 MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset); in resolveFrameIndex()
1128 MachineOperand *SOffset = TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in resolveFrameIndex()
1195 (uint64_t)TII->getNamedOperand(MI, AMDGPU::OpName::mask)->getImm()); in getNumSubRegsForSpillOp()
1507 const MachineOperand *Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::vdata); in buildMUBUFOffsetLoadStore()
1514 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)) in buildMUBUFOffsetLoadStore()
1515 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)) in buildMUBUFOffsetLoadStore()
1521 const MachineOperand *VDataIn = TII->getNamedOperand(*MI, in buildMUBUFOffsetLoadStore()
2418 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::mask)); in eliminateFrameIndex()
2466 const MachineOperand *VData = TII->getNamedOperand(*MI, in eliminateFrameIndex()
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H A DAMDGPUExportClustering.cpp34 unsigned Imm = TII->getNamedOperand(*MI, AMDGPU::OpName::tgt)->getImm(); in isPositionExport()
H A DSIModeRegister.cpp276 unsigned Dst = TII->getNamedOperand(MI, AMDGPU::OpName::simm16)->getImm(); in processBlockPhase1()
294 unsigned Val = TII->getNamedOperand(MI, AMDGPU::OpName::imm)->getImm(); in processBlockPhase1()
H A DAMDGPURewriteAGPRCopyMFMA.cpp145 TII.getNamedOperand(*CopySrcMI, AMDGPU::OpName::src2); in run()
H A DGCNCreateVOPD.cpp100 SII->getNamedOperand(*MI[CompIdx], SrcMods[CompSrcIdx]); in doReplace()
H A DSILowerControlFlow.cpp642 = TII->getNamedOperand(*Next, AMDGPU::OpName::src1)->getReg(); in optimizeEndCf()
652 Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::src1)->getReg(); in optimizeEndCf()
H A DSISchedule.td212 TII->getNamedOperand(*MI, AMDGPU::OpName::cbsz)->getImm() <= AMDGPU::MFMAScaleFormats::FP8_E5M2 ||
213 TII->getNamedOperand(*MI, AMDGPU::OpName::blgp)->getImm() <= AMDGPU::MFMAScaleFormats::FP8_E5M2
H A DSIInstrInfo.h1342 MachineOperand *getNamedOperand(MachineInstr &MI,
1346 const MachineOperand *getNamedOperand(const MachineInstr &MI, in getNamedOperand() function
1348 return getNamedOperand(const_cast<MachineInstr &>(MI), OperandName); in getNamedOperand()
H A DAMDGPUResourceUsageAnalysis.cpp441 TII->getNamedOperand(MI, AMDGPU::OpName::callee); in analyzeResourceUsage()
H A DSIPreEmitPeephole.cpp251 MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in optimizeSetGPR()
H A DAMDGPUMCInstLower.cpp257 TII->getNamedOperand(*MI, MI->mayLoad() ? AMDGPU::OpName::vdst in emitVGPRBlockComment()
H A DSIMemoryLegalizer.cpp938 MachineOperand *CPol = TII->getNamedOperand(*MI, AMDGPU::OpName::cpol); in enableNamedBit()
2239 MachineOperand *CPol = TII->getNamedOperand(*MI, OpName::cpol); in setTH()
2254 MachineOperand *CPol = TII->getNamedOperand(*MI, OpName::cpol); in setScope()
2546 MachineOperand *CPol = TII->getNamedOperand(*MI, OpName::cpol); in expandSystemScopeStore()

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