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Searched refs:getNamedOperand (Results 1 – 25 of 25) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPeepholeSDWA.cpp316 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) { in getSrcMods()
317 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) { in getSrcMods()
320 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) { in getSrcMods()
321 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers)) { in getSrcMods()
386 MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA()
387 MachineOperand *SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src0_sel); in convertToSDWA()
389 TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers); in convertToSDWA()
393 Src = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in convertToSDWA()
394 SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel); in convertToSDWA()
395 SrcMods = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers); in convertToSDWA()
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H A DGCNDPPCombine.cpp130 if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in isShrinkable()
223 auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask); in createDPPInst()
225 auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask); in createDPPInst()
242 if (auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst)) { in createDPPInst()
246 if (auto *SDst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::sdst)) { in createDPPInst()
260 TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg()), in createDPPInst()
278 auto *Mod0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0_modifiers); in createDPPInst()
290 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); in createDPPInst()
302 auto *Mod1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1_modifiers); in createDPPInst()
314 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst()
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H A DSILoadStoreOptimizer.cpp335 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm(); in getOpcodeWidth()
798 DMask = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); in setMI()
807 Format = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::format)->getImm(); in setMI()
814 CPol = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::cpol)->getImm(); in setMI()
927 const auto *TFEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::tfe); in dmasksCanBeCombined()
928 const auto *LWEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::lwe); in dmasksCanBeCombined()
1145 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) { in getDataRegClass()
1148 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::vdata)) { in getDataRegClass()
1151 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0)) { in getDataRegClass()
1154 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in getDataRegClass()
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H A DGCNHazardRecognizer.cpp179 const MachineOperand *RegOp = TII->getNamedOperand(RegInstr, in getHWReg()
833 TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in createsVALUHazard()
897 Register Def = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)->getReg(); in checkVALUHazards()
921 if (auto *DstSel = TII->getNamedOperand(MI, AMDGPU::OpName::dst_sel)) in checkVALUHazards()
926 !(TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers) in checkVALUHazards()
932 if (auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) { in checkVALUHazards()
989 MachineOperand *Src = TII.getNamedOperand(*VALU, AMDGPU::OpName::src0); in checkVALUHazards()
1056 TII->getNamedOperand(*RWLane, AMDGPU::OpName::src1); in checkRWLaneHazards()
1136 auto *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0); in fixVcmpxPermlaneHazards()
1216 const MachineOperand *SDST = TII->getNamedOperand(*MI, SDSTName); in fixSMEMtoVectorWriteHazards()
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H A DSIOptimizeExecMaskingPreRA.cpp154 MachineOperand *Op1 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src0); in optimizeVcndVcmpPair()
155 MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1); in optimizeVcndVcmpPair()
173 Op1 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src0); in optimizeVcndVcmpPair()
174 Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1); in optimizeVcndVcmpPair()
175 MachineOperand *CC = TII->getNamedOperand(*Sel, AMDGPU::OpName::src2); in optimizeVcndVcmpPair()
H A DSIOptimizeExecMasking.cpp583 MachineOperand *Src0 = TII->getNamedOperand(VCmp, AMDGPU::OpName::src0); in optimizeVCMPSaveExecSequence()
584 MachineOperand *Src1 = TII->getNamedOperand(VCmp, AMDGPU::OpName::src1); in optimizeVCMPSaveExecSequence()
604 if (auto *Mod = TII->getNamedOperand(VCmp, OperandName)) in optimizeVCMPSaveExecSequence()
653 MachineOperand *SaveExecSrc0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in tryRecordVCmpxAndSaveexecSequence()
677 MachineOperand *VCmpDest = TII->getNamedOperand(*VCmp, AMDGPU::OpName::sdst); in tryRecordVCmpxAndSaveexecSequence()
681 MachineOperand *Src0 = TII->getNamedOperand(*VCmp, AMDGPU::OpName::src0); in tryRecordVCmpxAndSaveexecSequence()
686 MachineOperand *Src1 = TII->getNamedOperand(*VCmp, AMDGPU::OpName::src1); in tryRecordVCmpxAndSaveexecSequence()
H A DSIInstrInfo.cpp369 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr); in getMemOperandsWithOffsetWidth()
370 OffsetOp = getNamedOperand(LdSt, AMDGPU::OpName::offset); in getMemOperandsWithOffsetWidth()
390 getNamedOperand(LdSt, AMDGPU::OpName::offset0); in getMemOperandsWithOffsetWidth()
392 getNamedOperand(LdSt, AMDGPU::OpName::offset1); in getMemOperandsWithOffsetWidth()
431 const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc); in getMemOperandsWithOffsetWidth()
435 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr); in getMemOperandsWithOffsetWidth()
439 getNamedOperand(LdSt, AMDGPU::OpName::offset); in getMemOperandsWithOffsetWidth()
442 getNamedOperand(LdSt, AMDGPU::OpName::soffset); in getMemOperandsWithOffsetWidth()
470 BaseOps.push_back(getNamedOperand(LdSt, AMDGPU::OpName::vaddr)); in getMemOperandsWithOffsetWidth()
482 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::sbase); in getMemOperandsWithOffsetWidth()
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H A DSIFoldOperands.cpp806 if (TII->getNamedOperand(*UseMI, AMDGPU::OpName::srsrc)->getReg() != in foldOperand()
813 *TII->getNamedOperand(*UseMI, AMDGPU::OpName::soffset); in foldOperand()
1316 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in tryFoldCndMask()
1317 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in tryFoldCndMask()
1527 if (!TII->getNamedOperand(MI, AMDGPU::OpName::clamp)->getImm()) in isClamp()
1531 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isClamp()
1532 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isClamp()
1544 = TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers)->getImm(); in isClamp()
1546 = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers)->getImm(); in isClamp()
1576 MachineOperand *DefClamp = TII->getNamedOperand(*Def, AMDGPU::OpName::clamp); in tryFoldClamp()
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H A DAMDGPUMacroFusion.cpp46 const MachineOperand *Src2 = TII.getNamedOperand(SecondMI, in shouldScheduleAdjacent()
H A DSIShrinkInstructions.cpp418 MachineOperand &Src0 = *TII->getNamedOperand(MI, AMDGPU::OpName::src0); in shrinkMadFma()
419 MachineOperand &Src1 = *TII->getNamedOperand(MI, AMDGPU::OpName::src1); in shrinkMadFma()
420 MachineOperand &Src2 = *TII->getNamedOperand(MI, AMDGPU::OpName::src2); in shrinkMadFma()
779 MachineOperand *Op = TII->getNamedOperand(MI, AMDGPU::OpName::sdst); in tryReplaceDeadSDST()
978 TII->getNamedOperand(MI, AMDGPU::OpName::src2); in runOnMachineFunction()
991 const MachineOperand *SDst = TII->getNamedOperand(MI, in runOnMachineFunction()
1005 const MachineOperand *Src2 = TII->getNamedOperand(MI, in runOnMachineFunction()
H A DSIRegisterInfo.cpp896 TII->getNamedOperand(MI, IsFlat ? AMDGPU::OpName::saddr in resolveFrameIndex()
899 MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset); in resolveFrameIndex()
915 MachineOperand *SOffset = TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in resolveFrameIndex()
1271 const MachineOperand *Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::vdata); in buildMUBUFOffsetLoadStore()
1278 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)) in buildMUBUFOffsetLoadStore()
1279 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)) in buildMUBUFOffsetLoadStore()
1285 const MachineOperand *VDataIn = TII->getNamedOperand(*MI, in buildMUBUFOffsetLoadStore()
2178 const MachineOperand *VData = TII->getNamedOperand(*MI, in eliminateFrameIndex()
2180 assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() == in eliminateFrameIndex()
2193 TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), in eliminateFrameIndex()
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H A DAMDGPUExportClustering.cpp35 unsigned Imm = TII->getNamedOperand(*MI, AMDGPU::OpName::tgt)->getImm(); in isPositionExport()
H A DSIModeRegister.cpp277 unsigned Dst = TII->getNamedOperand(MI, AMDGPU::OpName::simm16)->getImm(); in processBlockPhase1()
295 unsigned Val = TII->getNamedOperand(MI, AMDGPU::OpName::imm)->getImm(); in processBlockPhase1()
H A DSIInsertWaitcnts.cpp1223 TII->getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); in applyPreexistingWaitcnt()
1363 TII->getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); in applyPreexistingWaitcnt()
1371 TII->getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); in applyPreexistingWaitcnt()
1381 TII->getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); in applyPreexistingWaitcnt()
1875 TII->getNamedOperand(*It, AMDGPU::OpName::waitexp); in generateWaitcnt()
2048 int64_t Imm = TII->getNamedOperand(Inst, AMDGPU::OpName::waitexp)->getImm(); in updateEventWaitcntAfter()
2051 unsigned Imm = TII->getNamedOperand(Inst, AMDGPU::OpName::tgt)->getImm(); in updateEventWaitcntAfter()
H A DSILowerControlFlow.cpp633 = TII->getNamedOperand(*Next, AMDGPU::OpName::src1)->getReg(); in optimizeEndCf()
643 Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::src1)->getReg(); in optimizeEndCf()
H A DSIPreEmitPeephole.cpp249 MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in optimizeSetGPR()
H A DSIInstrInfo.h1271 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
1274 const MachineOperand *getNamedOperand(const MachineInstr &MI, in getNamedOperand() function
1276 return getNamedOperand(const_cast<MachineInstr &>(MI), OpName); in getNamedOperand()
H A DSILowerSGPRSpills.cpp359 int FI = TII->getNamedOperand(MI, AMDGPU::OpName::addr)->getIndex(); in runOnMachineFunction()
H A DSIMemoryLegalizer.cpp957 MachineOperand *CPol = TII->getNamedOperand(*MI, AMDGPU::OpName::cpol); in enableNamedBit()
2260 MachineOperand *CPol = TII->getNamedOperand(*MI, OpName::cpol); in setTH()
2275 MachineOperand *CPol = TII->getNamedOperand(*MI, OpName::cpol); in setScope()
2565 MachineOperand *CPol = TII->getNamedOperand(*MI, OpName::cpol); in expandSystemScopeStore()
H A DSIFixSGPRCopies.cpp355 TII->getNamedOperand(*MoveImm, AMDGPU::OpName::src0); in isSafeToFoldImmIntoCopy()
850 MachineOperand *SrcConst = TII->getNamedOperand(*DefMI, AMDGPU::OpName::src0); in tryMoveVGPRConstToSGPR()
H A DAMDGPUResourceUsageAnalysis.cpp517 TII->getNamedOperand(MI, AMDGPU::OpName::callee); in analyzeResourceUsage()
H A DSIISelLowering.cpp4421 if (MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0)) in emitGWSMemViolTestLoop()
4579 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx); in loadM0FromVGPR()
4622 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx); in setM0ToIndexFromSGPR()
4642 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx); in getIndirectSGPRIdx()
4663 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx); in emitIndirectSrc()
4664 Register SrcReg = TII->getNamedOperand(MI, AMDGPU::OpName::src)->getReg(); in emitIndirectSrc()
4665 int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm(); in emitIndirectSrc()
4749 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in emitIndirectDst()
4750 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx); in emitIndirectDst()
4751 const MachineOperand *Val = TII->getNamedOperand(MI, AMDGPU::OpName::val); in emitIndirectDst()
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H A DSIFrameLowering.cpp1380 TII->getNamedOperand(MI, AMDGPU::OpName::vdata)->getReg(); in processFunctionBeforeFrameFinalized()
/freebsd/contrib/llvm-project/clang/lib/AST/
H A DStmt.cpp579 int GCCAsmStmt::getNamedOperand(StringRef SymbolicName) const { in getNamedOperand() function in GCCAsmStmt
754 int N = getNamedOperand(SymbolicName); in AnalyzeAsmString()
/freebsd/contrib/llvm-project/clang/include/clang/AST/
H A DStmt.h3469 int getNamedOperand(StringRef SymbolicName) const;