Searched refs:getMaxNumSGPRs (Results 1 – 8 of 8) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNSubtarget.cpp | 429 unsigned MaxNumSGPRs = getMaxNumSGPRs(WavesPerEU.first, false); in getBaseMaxNumSGPRs() 430 unsigned MaxAddressableNumSGPRs = getMaxNumSGPRs(WavesPerEU.first, true); in getBaseMaxNumSGPRs() 455 if (Requested && Requested > getMaxNumSGPRs(WavesPerEU.first, false)) in getBaseMaxNumSGPRs() 471 unsigned GCNSubtarget::getMaxNumSGPRs(const MachineFunction &MF) const { in getMaxNumSGPRs() function in GCNSubtarget 503 unsigned GCNSubtarget::getMaxNumSGPRs(const Function &F) const { in getMaxNumSGPRs() function in GCNSubtarget
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| H A D | GCNSubtarget.h | 1524 unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const { in getMaxNumSGPRs() function 1525 return AMDGPU::IsaInfo::getMaxNumSGPRs(this, WavesPerEU, Addressable); in getMaxNumSGPRs() 1557 unsigned getMaxNumSGPRs(const MachineFunction &MF) const; 1567 unsigned getMaxNumSGPRs(const Function &F) const;
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| H A D | GCNRegPressure.cpp | 121 unsigned MaxSGPRs = ST.getMaxNumSGPRs(MF); in less() 372 setRegLimits(ST.getMaxNumSGPRs(F), ST.getMaxNumVGPRs(F), MF); in GCNRPTarget() 388 setRegLimits(ST.getMaxNumSGPRs(Occupancy, /*Addressable=*/false), in GCNRPTarget()
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| H A D | GCNSchedStrategy.cpp | 99 std::min(ST.getMaxNumSGPRs(TargetOccupancy, true), SGPRExcessLimit); in initialize() 1331 unsigned MaxSGPRs = ST.getMaxNumSGPRs(MF); in checkScheduling() 1718 const unsigned MaxSGPRsNoSpill = ST.getMaxNumSGPRs(F); in canIncreaseOccupancyOrReduceSpill() 1721 ST.getMaxNumSGPRs(DAG.MinOccupancy + 1, false); in canIncreaseOccupancyOrReduceSpill()
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| H A D | SIRegisterInfo.cpp | 563 unsigned BaseIdx = alignDown(ST.getMaxNumSGPRs(MF), Align) - Align; in getAlignedHighSGPRForRC() 689 unsigned MaxNumSGPRs = ST.getMaxNumSGPRs(MF); in getReservedRegs() 3760 return std::min(ST.getMaxNumSGPRs(MinOcc, true), ST.getMaxNumSGPRs(MF)); in getRegPressureLimit() 4026 return ArrayRef(AMDGPU::SGPR_128RegClass.begin(), ST.getMaxNumSGPRs(MF) / 4); in getAllSGPR128() 4031 return ArrayRef(AMDGPU::SGPR_64RegClass.begin(), ST.getMaxNumSGPRs(MF) / 2); in getAllSGPR64() 4036 return ArrayRef(AMDGPU::SGPR_32RegClass.begin(), ST.getMaxNumSGPRs(MF)); in getAllSGPR32()
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| H A D | SIISelLowering.cpp | 16757 unsigned MaxNumSGPRs = ST.getMaxNumSGPRs(MF); in finalizeLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.h | 277 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
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| H A D | AMDGPUBaseInfo.cpp | 1236 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, in getMaxNumSGPRs() function
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