Searched refs:getLdStBaseOp (Results 1 – 4 of 4) sorted by relevance
38 const MachineOperand &Base0 = AArch64InstrInfo::getLdStBaseOp(MI0); in mayOverlapWrite()39 const MachineOperand &Base1 = AArch64InstrInfo::getLdStBaseOp(MI1); in mayOverlapWrite()
795 AArch64InstrInfo::getLdStBaseOp(MI).getReg() == AArch64::SP) in isMergeableLdStUpdate()877 MergeForward ? AArch64InstrInfo::getLdStBaseOp(*MergeMI) in mergeNarrowZeroStores()878 : AArch64InstrInfo::getLdStBaseOp(*I); in mergeNarrowZeroStores()1120 MergeForward ? AArch64InstrInfo::getLdStBaseOp(*Paired) in mergePairedInsns()1121 : AArch64InstrInfo::getLdStBaseOp(*I); in mergePairedInsns()1567 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(LoadMI).getReg(); in findMatchingStore()1596 BaseReg == AArch64InstrInfo::getLdStBaseOp(MI).getReg() && in findMatchingStore()1973 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(FirstMI).getReg(); in findMatchingInsn()2019 Register MIBaseReg = AArch64InstrInfo::getLdStBaseOp(MI).getReg(); in findMatchingInsn()2052 AArch64InstrInfo::getLdStBaseOp(MI).getReg()); in findMatchingInsn()[all …]
249 static const MachineOperand &getLdStBaseOp(const MachineInstr &MI);
4674 const MachineOperand &AArch64InstrInfo::getLdStBaseOp(const MachineInstr &MI) { in getLdStBaseOp() function in AArch64InstrInfo