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Searched refs:getLatency (Results 1 – 25 of 26) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DScheduleDAG.cpp84 dbgs() << " Latency=" << getLatency(); in dump()
90 dbgs() << " Latency=" << getLatency(); in dump()
93 dbgs() << " Latency=" << getLatency(); in dump()
116 if (PredDep.getLatency() < D.getLatency()) { in addPred()
123 SuccDep.setLatency(D.getLatency()); in addPred()
127 PredDep.setLatency(D.getLatency()); in addPred()
276 PredSU->Depth + PredDep.getLatency()); in ComputeDepth()
307 SuccSU->Height + SuccDep.getLatency()); in ComputeHeight()
H A DLatencyPriorityQueue.cpp36 unsigned LHSLatency = PQ->getLatency(LHSNum); in operator ()()
37 unsigned RHSLatency = PQ->getLatency(RHSNum); in operator ()()
H A DVLIWMachineScheduler.cpp97 if (S.getSUnit() == SUu && S.getLatency() > 0) in hasDependence()
310 unsigned MinLatency = PI.getLatency(); in releaseTopNode()
328 unsigned MinLatency = I->getLatency(); in releaseBottomNode()
709 PI.getLatency() == 0 && in SchedulingCost()
718 SI.getLatency() == 0 && in SchedulingCost()
734 if (PI.getLatency() > 0 && in SchedulingCost()
742 if (SI.getLatency() > 0 && in SchedulingCost()
H A DWindowScheduler.cpp441 ExpectCycle = std::max(ExpectCycle, PredCycle + (int)Pred.getLatency()); in calculateMaxCycle()
503 if (DefCycle + (int)Succ.getLatency() <= CurrentII) in calculateStallCycle()
513 int StallCycle = DefCycle + (int)Succ.getLatency() - CurrentII - UseCycle; in calculateStallCycle()
H A DMachineCombiner.cpp97 unsigned getLatency(MachineInstr *Root, MachineInstr *NewRoot,
268 unsigned MachineCombiner::getLatency(MachineInstr *Root, MachineInstr *NewRoot, in getLatency() function in MachineCombiner
326 NewRootLatency += getLatency(&MI, NewRoot, BlockTrace); in getLatenciesForInstrSequences()
H A DMachinePipeliner.cpp1830 unsigned Delay = Nodes.getLatency(); in calculateRecMII()
2079 if (IE.getLatency() == 0) in computeNodeFunctions()
2084 asap = std::max(asap, (int)(getASAP(Pred) + IE.getLatency() - in computeNodeFunctions()
2101 if (OE.getLatency() == 0) in computeNodeFunctions()
2106 alap = std::min(alap, (int)(getALAP(Succ) - OE.getLatency() + in computeNodeFunctions()
3270 int EarlyStart = cycle + IE.getLatency() - IE.getDistance() * II; in computeStart()
3283 int LateStart = cycle - OE.getLatency() + OE.getDistance() * II; in computeStart()
4261 int MaxLateStart = CycleDst + Edge.getDistance() * II - Edge.getLatency(); in isValidSchedule()
H A DCriticalAntiDepBreaker.cpp146 unsigned PredLatency = P.getLatency(); in CriticalPathStep()
H A DAggressiveAntiDepBreaker.cpp275 unsigned PredLatency = Pred.getLatency(); in CriticalPathStep()
H A DMachineScheduler.cpp959 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency()) in releaseSucc()
960 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency(); in releaseSucc()
994 if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency()) in releasePred()
995 PredSU->BotReadyCycle = SU->BotReadyCycle + PredEdge->getLatency(); in releasePred()
/freebsd/contrib/llvm-project/llvm/lib/MCA/
H A DInstruction.cpp57 CyclesLeft = getLatency(); in onInstructionIssued()
126 dbgs() << "{ OpIdx=" << WD->OpIndex << ", Lat=" << getLatency() << ", RegID " in dump()
178 CyclesLeft = getLatency(); in execute()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLatencyMutations.cpp643 setBidirLatencies(ISU, Dep, Dep.getLatency() + 1); in modifyBypasses()
650 setBidirLatencies(ISU, Dep, Dep.getLatency() + 1); in modifyBypasses()
676 Lat = std::min(3u, Dep.getLatency() + Lat); in modifyBypasses()
677 setBidirLatencies(ISU, Dep, std::max(Dep.getLatency(), Lat)); in modifyBypasses()
894 setBidirLatencies(ISU, Dep, Dep.getLatency() + 1); in modifyBypasses()
897 setBidirLatencies(ISU, Dep, Dep.getLatency() + 1); in modifyBypasses()
904 setBidirLatencies(ISU, Dep, Dep.getLatency() - 1); in modifyBypasses()
914 setBidirLatencies(ISU, Dep, std::max(0, signed(Dep.getLatency()) + ALat)); in modifyBypasses()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonHazardRecognizer.cpp149 if (S.isAssignedRegDep() && S.getLatency() == 0 && in EmitInstruction()
164 if (S.isAssignedRegDep() && S.getLatency() == 0 && in EmitInstruction()
H A DHexagonSubtarget.cpp270 if (SI.getKind() != SDep::Order || SI.getLatency() != 0) in apply()
508 int Latency = Dep.getLatency(); in adjustSchedDependency()
599 F->setLatency(I.getLatency()); in restoreLatency()
623 if (I.isAssignedRegDep() && I.getLatency() == 0 && in getZeroLatency()
H A DHexagonVLIWPacketizer.cpp1914 if ((Pred.getLatency() == 0 && Pred.isAssignedRegDep()) || in calcStall()
1924 if (Pred.getSUnit() == SUJ && Pred.getLatency() > 1) in calcStall()
1925 return Pred.getLatency(); in calcStall()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachinePipeliner.h157 unsigned getLatency() const { return Pred.getLatency(); } in getLatency() function
525 if (DU + Succ.getLatency() > DV) in NodeSet()
526 DV = DU + Succ.getLatency(); in NodeSet()
588 unsigned getLatency() { return Latency; } in getLatency() function
H A DLatencyPriorityQueue.h68 unsigned getLatency(unsigned NodeNum) const { in getLatency() function
H A DResourcePriorityQueue.h93 unsigned getLatency(unsigned NodeNum) const { in getLatency() function
H A DScheduleDAG.h142 unsigned getLatency() const { in getLatency() function
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/
H A DInstruction.h264 unsigned getLatency() const { return WD->Latency; } in getLatency() function
296 return !CyclesLeft || CyclesLeft < getLatency(); in isReady()
542 unsigned getLatency() const { return Desc.MaxLatency; } in getLatency() function
/freebsd/contrib/llvm-project/llvm/lib/MCA/Stages/
H A DInOrderIssueStage.cpp89 unsigned FirstWBCycle = IR.getInstruction()->getLatency(); in findFirstWriteBackCycle()
93 CyclesLeft = WS.getLatency(); in findFirstWriteBackCycle()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGVLIW.cpp120 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency()); in releaseSucc()
H A DResourcePriorityQueue.cpp189 unsigned LHSLatency = PQ->getLatency(LHSNum); in operator ()()
190 unsigned RHSLatency = PQ->getLatency(RHSNum); in operator ()()
/freebsd/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp302 if (OtherWS->getLatency() > WS.getLatency()) { in addRegisterWrite()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNILPSched.cpp280 PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge.getLatency()); in releasePredecessors()
H A DGCNSubtarget.cpp575 } else if (Dep.getLatency() == 0 && Dep.getReg() == AMDGPU::VCC_LO) { in adjustSchedDependency()

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