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Searched refs:getKillRegState (Results 1 – 25 of 74) sorted by relevance

123

/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp163 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandArith()
164 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandArith()
169 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandArith()
170 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expandArith()
197 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLogic()
198 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandLogic()
206 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandLogic()
207 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expandLogic()
258 .addReg(DstLoReg, getKillRegState(SrcIsKill)) in expandLogicImm()
272 .addReg(DstHiReg, getKillRegState(SrcIsKill)) in expandLogicImm()
[all …]
H A DAVRInstrInfo.cpp49 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
63 .addReg(SrcHi, getKillRegState(KillSrc) | RegState::Undef); in copyPhysReg()
65 .addReg(SrcLo, getKillRegState(KillSrc) | RegState::Undef); in copyPhysReg()
68 .addReg(SrcLo, getKillRegState(KillSrc) | RegState::Undef); in copyPhysReg()
70 .addReg(SrcHi, getKillRegState(KillSrc) | RegState::Undef); in copyPhysReg()
85 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
156 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp57 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
72 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
97 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
100 .addReg(TmpReg, getKillRegState(true)) in copyPhysReg()
108 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
137 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
H A DMLxExpansionPass.cpp291 .addReg(Src1Reg, getKillRegState(Src1Kill)) in ExpandFPMLxInstruction()
292 .addReg(Src2Reg, getKillRegState(Src2Kill)); in ExpandFPMLxInstruction()
302 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
303 .addReg(AccReg, getKillRegState(AccKill)); in ExpandFPMLxInstruction()
305 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
H A DARMLoadStoreOptimizer.cpp744 .addReg(Base, getKillRegState(KillOldBase)); in CreateLoadStoreMulti()
747 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
757 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
763 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
768 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
810 .addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti()
819 MIB.addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti()
825 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second)); in CreateLoadStoreMulti()
849 MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second)) in CreateLoadStoreDouble()
850 .addReg(Regs[1].first, getKillRegState(Regs[1].second)); in CreateLoadStoreDouble()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp301 TmpReg, getKillRegState(true)); in processSTVM()
305 build(VE::SVMmr, TmpReg).addReg(SrcReg, getKillRegState(isKill)).addImm(3); in processSTVM()
348 build(VE::LVMir, DestReg).addImm(i).addReg(TmpReg, getKillRegState(true)); in processLDVM()
352 .addReg(TmpReg, getKillRegState(true)) in processLDVM()
357 .addReg(TmpReg, getKillRegState(true)) in processLDVM()
383 TmpReg, getKillRegState(true)); in processSTVM512()
394 TmpReg, getKillRegState(true)); in processSTVM512()
429 .addReg(TmpReg, getKillRegState(true)) in processLDVM512()
439 .addReg(TmpReg, getKillRegState(true)) in processLDVM512()
447 .addReg(TmpReg, getKillRegState(true)) in processLDVM512()
H A DVEInstrInfo.cpp365 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
383 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
384 .addReg(SubTmp, getKillRegState(true)); in copyPhysReg()
389 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
481 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
488 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
495 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
502 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
509 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
516 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
[all …]
H A DVEISelLowering.cpp2029 .addReg(Tmp1, getKillRegState(true)) in prepareMBB()
2033 .addReg(Tmp2, getKillRegState(true)) in prepareMBB()
2045 .addReg(Tmp1, getKillRegState(true)) in prepareMBB()
2048 .addReg(Tmp2, getKillRegState(true)) in prepareMBB()
2090 .addReg(Tmp1, getKillRegState(true)) in prepareSymbol()
2094 .addReg(Tmp2, getKillRegState(true)) in prepareSymbol()
2110 .addReg(Tmp1, getKillRegState(true)) in prepareSymbol()
2114 .addReg(Tmp2, getKillRegState(true)) in prepareSymbol()
2117 .addReg(Tmp3, getKillRegState(true)) in prepareSymbol()
2133 .addReg(Tmp1, getKillRegState(true)) in prepareSymbol()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp455 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
463 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
467 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
478 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
495 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
499 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
545 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
548 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
551 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
554 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp38 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
41 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
138 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
143 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp430 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
486 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
491 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
502 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
510 .addReg(DestReg, getKillRegState(true)) in copyPhysReg()
511 .addReg(DestReg, getKillRegState(true)) in copyPhysReg()
512 .addReg(SrcReg, getKillRegState(true)); in copyPhysReg()
563 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
H A DCSKYRegisterInfo.cpp210 .addReg(NewReg, getKillRegState(true)) in eliminateFrameIndex()
230 .addReg(NewReg, getKillRegState(true)) in eliminateFrameIndex()
231 .addReg(NewReg, getKillRegState(true)) in eliminateFrameIndex()
240 .addReg(NewReg, getKillRegState(true)) in eliminateFrameIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h153 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
161 return MIB.addReg(Reg1, getKillRegState(isKill1), SubReg1) in addRegReg()
163 .addReg(Reg2, getKillRegState(isKill2), SubReg2) in addRegReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp48 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
56 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
64 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
73 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
80 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
86 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
110 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
144 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp301 .addReg(SrcReg, getKillRegState(KillSrcReg)) in adjustReg()
324 .addReg(SrcReg, getKillRegState(KillSrcReg)) in adjustReg()
343 .addReg(SrcReg, getKillRegState(KillSrcReg)) in adjustReg()
372 .addReg(SrcReg, getKillRegState(KillSrcReg)) in adjustReg()
387 .addReg(SrcReg, getKillRegState(KillSrcReg)) in adjustReg()
463 .addReg(Base, getKillRegState(I == NF - 1)) in lowerVSPILL()
468 .addReg(Base, getKillRegState(I != 0 || IsBaseKill)) in lowerVSPILL()
469 .addReg(VL, getKillRegState(I == NF - 2)); in lowerVSPILL()
541 .addReg(Base, getKillRegState(I == NF - 1)) in lowerVRELOAD()
545 .addReg(Base, getKillRegState(I != 0 || IsBaseKill)) in lowerVRELOAD()
[all …]
H A DRISCVExpandPseudoInsts.cpp303 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill())) in expandMV_FPR16INX()
320 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill())) in expandMV_FPR32INX()
342 .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill())) in expandRV32ZdinxStore()
351 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill())) in expandRV32ZdinxStore()
357 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill())) in expandRV32ZdinxStore()
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp72 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
109 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
143 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPImmInst()
188 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPConstInst()
H A DXCoreInstrInfo.cpp337 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
349 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
370 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp276 .addReg(Src, getKillRegState(IsKill)); in insertCopy()
361 .addReg(Src0, getKillRegState(KillSrc0), SubReg0) in transformInstruction()
362 .addReg(Src1, getKillRegState(KillSrc1), SubReg1); in transformInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp49 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
53 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
98 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp704 .addReg(VReg1, getKillRegState(true)) in generateLoadForNewConst()
919 .addReg(RegX, getKillRegState(KillX)) in reassociateFMA()
920 .addReg(RegM21, getKillRegState(KillM21)) in reassociateFMA()
921 .addReg(RegM22, getKillRegState(KillM22)); in reassociateFMA()
924 .addReg(RegY, getKillRegState(KillY)) in reassociateFMA()
925 .addReg(RegM31, getKillRegState(KillM31)) in reassociateFMA()
926 .addReg(RegM32, getKillRegState(KillM32)); in reassociateFMA()
936 .addReg(NewVRB, getKillRegState(true)) in reassociateFMA()
937 .addReg(NewVRA, getKillRegState(true)); in reassociateFMA()
956 .addReg(RegM11, getKillRegState(KillM11)) in reassociateFMA()
[all …]
H A DPPCRegisterInfo.cpp773 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); in lowerDynamicAlloc()
781 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); in lowerDynamicAlloc()
861 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) in prepareDynamicAlloca()
878 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) in prepareDynamicAlloca()
978 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); in lowerCRSpilling()
1118 getKillRegState(MI.getOperand(0).isKill())); in lowerCRBitSpilling()
1134 getKillRegState(MI.getOperand(0).isKill())); in lowerCRBitSpilling()
1143 RegState::Implicit | getKillRegState(MI.getOperand(0).isKill())); in lowerCRBitSpilling()
1260 getKillRegState(IsKilled)), in spillRegPair()
1266 getKillRegState(IsKilled)), in spillRegPair()
[all …]
H A DPPCFrameLowering.cpp812 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
847 .addReg(ScratchReg, getKillRegState(!HasROPProtect)) in emitPrologue()
865 .addReg(ScratchReg, getKillRegState(true)) in emitPrologue()
878 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
986 .addReg(TOCReg, getKillRegState(true)) in emitPrologue()
1786 .addReg(TempReg, getKillRegState(i == e-1)); in emitEpilogue()
1862 .addReg(TempReg, getKillRegState(i == e-1)); in emitEpilogue()
2482 getKillRegState(true)), in spillCalleeSavedRegisters()
2499 .addReg(VSR.first, getKillRegState(true)) in spillCalleeSavedRegisters()
2500 .addReg(VSR.second, getKillRegState(true)); in spillCalleeSavedRegisters()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetFrameLoweringImpl.cpp197 .addReg(Reg, getKillRegState(true)); in spillCalleeSavedRegister()
212 .addReg(CS.getDstReg(), getKillRegState(true)); in restoreCalleeSavedRegister()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp110 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
131 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4) in copyPhysReg()
137 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
178 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
284 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) in storeRegToStack()
723 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill())); in expandPseudoMTLoHi()
724 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill())); in expandPseudoMTLoHi()
734 unsigned KillSrc = getKillRegState(Src.isKill()); in expandCvtFPInt()

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