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Searched refs:getID (Results 1 – 25 of 197) sorted by relevance

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/freebsd/contrib/llvm-project/clang/lib/Analysis/
H A DIntervalPartition.cpp34 static unsigned getID(const CFGBlock &B) { return B.getBlockID(); } in getID() function
35 static unsigned getID(const CFGIntervalNode &I) { return I.ID; } in getID() function
44 Partitioned.set(getID(*Header)); in buildInterval()
54 if (auto SID = getID(*S); !Partitioned.test(SID)) { in buildInterval()
72 auto ID = getID(*B); in buildInterval()
86 if (auto SID = getID(*S); in buildInterval()
121 assert(getID(*N) < Index.size()); in fillIntervalNode()
122 Index[getID(*N)] = &Interval; in fillIntervalNode()
165 if (Partitioned.test(getID(*B))) in partitionIntoIntervalsImpl()
182 assert(getID(*P) < NumBlockIDs); in partitionIntoIntervalsImpl()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp60 RegLimit[RC->getID()] = TRI->getRegPressureLimit(RC, *IS->MF); in ResourcePriorityQueue()
95 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValPredInSU()
133 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValSuccInSU()
329 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
340 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
360 RegBalance += rawRegPressureDelta(SU, RC->getID()); in regPressureDelta()
364 if ((RegPressure[RC->getID()] + in regPressureDelta()
365 rawRegPressureDelta(SU, RC->getID()) > 0) && in regPressureDelta()
366 (RegPressure[RC->getID()] + in regPressureDelta()
367 rawRegPressureDelta(SU, RC->getID()) >= RegLimit[RC->getID()])) in regPressureDelta()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterBank.cpp44 assert(RBI.getMaximumSize(getID()) >= TRI.getRegSizeInBits(SubRC) && in verify()
53 return (CoveredClasses[RC.getID() / 32] & (1U << RC.getID() % 32)) != 0; in verify()
60 assert((OtherRB.getID() != getID() || &OtherRB == this) && in verify()
81 OS << "(ID:" << getID() << ")\n" in operator ==()
H A DVLIWMachineScheduler.cpp605 << ((Q.getID() == TopQID) ? "(top|" : "(bot|")); in SchedulingCost()
614 if (Q.getID() == TopQID) { in SchedulingCost()
657 if (Q.getID() == TopQID) { in SchedulingCost()
693 if (IsAvailableAmt && pressureChange(SU, Q.getID() != TopQID) > 0 && in SchedulingCost()
706 if (Q.getID() == TopQID && getWeakLeft(SU, true) == 0) { in SchedulingCost()
715 } else if (Q.getID() == BotQID && getWeakLeft(SU, false) == 0) { in SchedulingCost()
732 if (Q.getID() == TopQID) { in SchedulingCost()
800 if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum) || in pickNodeFromQueue()
801 (Q.getID() == BotQID && (*I)->NodeNum > Candidate.SU->NodeNum)) { in pickNodeFromQueue()
822 unsigned CurrWeak = getWeakLeft(*I, (Q.getID() == TopQID)); in pickNodeFromQueue()
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H A DRegisterBankInfo.cpp64 assert(RegBanks[Idx]->getID() == Idx && in RegisterBankInfo()
74 assert(Idx == RegBank.getID() && in verify()
269 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); in hashPartialMapping()
528 assert(RBI.getMaximumSize(RegBank->getID()) >= Length && in verify()
652 OS << "ID: " << getID() << " Cost: " << getCost() << " Mapping: "; in print()
792 OS << "Mapping ID: " << getInstrMapping().getID() << ' '; in print()
/freebsd/contrib/llvm-project/clang/lib/Frontend/
H A DTextDiagnosticPrinter.cpp54 if (Info.getID() == diag::fatal_too_many_errors) { in printDiagnosticOptions()
70 Info.getID()) && in printDiagnosticOptions()
72 Info.getID())) { in printDiagnosticOptions()
79 Info.getID()); in printDiagnosticOptions()
93 DiagnosticIDs::getCategoryNumberForDiag(Info.getID()); in printDiagnosticOptions()
/freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/
H A DHLSL.cpp289 if (A->getOption().getID() == options::OPT_dxil_validator_version) { in TranslateArgs()
294 if (A->getOption().getID() == options::OPT_dxc_entrypoint) { in TranslateArgs()
300 if (A->getOption().getID() == options::OPT_dxc_rootsig_ver) { in TranslateArgs()
307 if (A->getOption().getID() == options::OPT__SLASH_O) { in TranslateArgs()
319 if (A->getOption().getID() == options::OPT_emit_pristine_llvm) { in TranslateArgs()
327 if (A->getOption().getID() == options::OPT_dxc_hlsl_version) { in TranslateArgs()
342 if (A->getOption().getID() == options::OPT_dxc_gis) { in TranslateArgs()
349 if (A->getOption().getID() == options::OPT_fvk_use_dx_layout) { in TranslateArgs()
355 if (A->getOption().getID() == options::OPT_fvk_use_scalar_layout) { in TranslateArgs()
361 if (A->getOption().getID() == options::OPT_fvk_use_gl_layout) { in TranslateArgs()
H A DSYCL.cpp101 if (Opt.getID() == options::OPT_fsanitize_EQ && in TranslateArgs()
111 DAL->eraseArg(Opt.getID()); in TranslateArgs()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp195 assert((RegBank->getID() == ARM::GPRRegBankID || in guessRegClass()
196 RegBank->getID() == ARM::FPRRegBankID) && in guessRegClass()
199 if (RegBank->getID() == ARM::FPRRegBankID) { in guessRegClass()
245 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
250 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
255 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
277 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
282 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
287 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectUnmergeValues()
520 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { in validReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp87 switch (RC->getID()) { in getCallerSavedRegs()
358 if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID()) in shouldCoalesce()
360 bool SmallSrc = SrcRC->getID() == Hexagon::HvxVRRegClass.getID(); in shouldCoalesce()
361 bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID(); in shouldCoalesce()
424 switch (RC.getID()) { in getHexagonSubRegIndex()
H A DHexagonMachineScheduler.cpp58 if (Q.getID() == TopQID && in SchedulingCost()
62 } else if (Q.getID() == BotQID && in SchedulingCost()
/freebsd/contrib/llvm-project/llvm/include/llvm/Option/
H A DOptSpecifier.h31 unsigned getID() const { return ID; } in getID() function
33 bool operator==(OptSpecifier Opt) const { return ID == Opt.getID(); }
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIMachineScheduler.cpp513 unsigned PredID = Pred->getID(); in addPred()
517 if (PredID == P->getID()) in addPred()
525 return PredID == S.first->getID(); in addPred()
532 unsigned SuccID = Succ->getID(); in addSucc()
536 if (SuccID == S.first->getID()) { in addSucc()
548 [=](SIScheduleBlock *P) { return SuccID == P->getID(); }) && in addSucc()
623 return CurrentBlocks[Node2CurrentBlock[SU->NodeNum]]->getID() == ID; in isSUInBlock()
1255 if (!--TopDownBlock2Index[Pred->getID()]) in topologicalSort()
1256 WorkList.push_back(Pred->getID()); in topologicalSort()
1265 assert(TopDownBlock2Index[i] > TopDownBlock2Index[Pred->getID()] && in topologicalSort()
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H A DAMDGPUSplitModule.cpp387 unsigned getID() const { return ID; } in getID() function in llvm::__anon00e757230111::SplitGraph::Node
441 visitAllDependencies([&](const Node &N) { BV.set(N.getID()); }); in getDependencies()
611 if (!NodesReachableByKernels.test(N->getID())) in buildGraph()
627 if (N->getID() != (ExpectedID++)) { in verifyGraph()
637 if (&getNode(N->getID()) != N) { in verifyGraph()
736 assert(&getNode(N->getID()) == N); in getNode()
1013 NodeEC.insert(N->getID()); in setupWorkList()
1016 NodeEC.unionSets(N->getID(), Dep.getID()); in setupWorkList()
1440 dbgs() << " - [" << N->getID() << "]: " << N->getName() << " " in splitAMDGPUModule()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DUtils.cpp22 return std::tuple(Rec1->getValueAsString("Name"), Rec1->getID()) < in operator ()()
23 std::tuple(Rec2->getValueAsString("Name"), Rec2->getID()); in operator ()()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp177 if (RB.getID() == X86::GPRRegBankID) { in getRegClass()
187 if (RB.getID() == X86::VECRRegBankID) { in getRegClass()
202 if (RB.getID() == X86::PSRRegBankID) { in getRegClass()
294 if (DstSize > SrcSize && SrcRegBank.getID() == X86::GPRRegBankID && in selectCopy()
295 DstRegBank.getID() == X86::GPRRegBankID) { in selectCopy()
330 if (SrcRegBank.getID() == X86::GPRRegBankID && in selectCopy()
331 DstRegBank.getID() == X86::GPRRegBankID && SrcSize > DstSize && in selectCopy()
458 if (Ty.isPointer() && X86::GPRRegBankID == RB.getID()) { in getPtrLoadStoreOp()
482 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
485 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
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/freebsd/contrib/llvm-project/llvm/lib/Option/
H A DOption.cpp103 if (getID() == Opt.getID()) in matches()
246 if (getID() == UnaliasedOption.getID()) in accept()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp
/freebsd/contrib/llvm-project/lld/MachO/
H A DDriver.cpp71 switch (outputArg->getOption().getID()) { in getOutputType()
233 switch (arg->getOption().getID()) { in getLTOCachePolicy()
702 assert(arg->getOption().getID() == OPT_platform_version); in parsePlatformVersion()
866 if (arg->getOption().getID() == OPT_objc_stubs_small) { in getObjCStubsMode()
879 if (opt.getGroup().getID() == OPT_grp_deprecated) { in warnIfDeprecatedOption()
888 switch (opt.getGroup().getID()) { in warnIfUnimplementedOption()
1142 if (arg && arg->getOption().getID() == OPT_objc_relative_method_lists) in shouldEmitRelativeMethodLists()
1144 if (arg && arg->getOption().getID() == OPT_no_objc_relative_method_lists) in shouldEmitRelativeMethodLists()
1230 switch (opt.getID()) { in createFiles()
1267 addLibrary(arg->getValue(), opt.getID() == OPT_needed_l, in createFiles()
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/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DMemorySSA.h219 inline unsigned getID() const;
330 OptimizedID = DMA->getID();
338 return getDefiningAccess() && OptimizedID == getDefiningAccess()->getID();
394 OptimizedID = MA->getID();
402 return getOptimized() && OptimizedID == getOptimized()->getID();
412 unsigned getID() const { return ID; }
634 unsigned getID() const { return ID; }
663 inline unsigned MemoryAccess::getID() const {
667 return MD->getID();
668 return cast<MemoryPhi>(this)->getID();
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.cpp76 assert(getMaximumSize(RBGPR.getID()) == 128 && in AArch64RegisterBankInfo()
85 assert(getMaximumSize(RBFPR.getID()) == 512 && in AArch64RegisterBankInfo()
90 assert(getMaximumSize(RBCCR.getID()) == 32 && in AArch64RegisterBankInfo()
244 switch (RC.getID()) { in getRegBankFromRegClass()
370 assert((OpdMapper.getInstrMapping().getID() >= 1 && in applyMappingImpl()
371 OpdMapper.getInstrMapping().getID() <= 4) && in applyMappingImpl()
735 getCopyMapping(DstRB->getID(), SrcRB->getID(), Size), in getInstrMapping()
754 getCopyMapping(DstRB.getID(), SrcRB.getID(), Size), in getInstrMapping()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h74 unsigned getID() const { return MC->getID(); } in getID() function
132 unsigned ID = RC->getID(); in hasSubClassEq()
848 return RCInfos[getNumRegClasses() * HwMode + RC.getID()]; in getRegClassInfo()
1385 bool isValid() const { return getID() != NumRegClasses; } in isValid()
1388 unsigned getID() const { return ID; } in getID() function
H A DStackMaps.h48 uint64_t getID() const { return MI->getOperand(IDPos).getImm(); } in getID() function
102 uint64_t getID() const { return getMetaOper(IDPos).getImm(); } in getID() function
205 uint64_t getID() const { return MI->getOperand(NumDefs + IDPos).getImm(); } in getID() function
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCRegisterBankInfo.cpp35 switch (RC.getID()) { in getRegBankFromRegClass()
214 MappingID, Cost, getCopyMapping(DstRB.getID(), SrcRB.getID(), DstSize), in getInstrMapping()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DDAGISelEmitter.cpp130 return LHS->getID() < RHS->getID(); in operator ()()

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