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Searched refs:getID (Results 1 – 25 of 185) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp60 RegLimit[RC->getID()] = TRI->getRegPressureLimit(RC, *IS->MF); in ResourcePriorityQueue()
95 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValPredInSU()
133 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValSuccInSU()
329 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
340 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
360 RegBalance += rawRegPressureDelta(SU, RC->getID()); in regPressureDelta()
364 if ((RegPressure[RC->getID()] + in regPressureDelta()
365 rawRegPressureDelta(SU, RC->getID()) > 0) && in regPressureDelta()
366 (RegPressure[RC->getID()] + in regPressureDelta()
367 rawRegPressureDelta(SU, RC->getID()) >= RegLimit[RC->getID()])) in regPressureDelta()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterBank.cpp44 assert(RBI.getMaximumSize(getID()) >= TRI.getRegSizeInBits(SubRC) && in verify()
53 return (CoveredClasses[RC.getID() / 32] & (1U << RC.getID() % 32)) != 0; in verify()
60 assert((OtherRB.getID() != getID() || &OtherRB == this) && in verify()
81 OS << "(ID:" << getID() << ")\n" in operator ==()
H A DVLIWMachineScheduler.cpp608 << ((Q.getID() == TopQID) ? "(top|" : "(bot|")); in SchedulingCost()
617 if (Q.getID() == TopQID) { in SchedulingCost()
660 if (Q.getID() == TopQID) { in SchedulingCost()
696 if (IsAvailableAmt && pressureChange(SU, Q.getID() != TopQID) > 0 && in SchedulingCost()
709 if (Q.getID() == TopQID && getWeakLeft(SU, true) == 0) { in SchedulingCost()
718 } else if (Q.getID() == BotQID && getWeakLeft(SU, false) == 0) { in SchedulingCost()
735 if (Q.getID() == TopQID) { in SchedulingCost()
803 if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum) || in pickNodeFromQueue()
804 (Q.getID() == BotQID && (*I)->NodeNum > Candidate.SU->NodeNum)) { in pickNodeFromQueue()
825 unsigned CurrWeak = getWeakLeft(*I, (Q.getID() == TopQID)); in pickNodeFromQueue()
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H A DInitUndef.cpp178 LLVM_DEBUG(dbgs() << "Register Class ID" << SubRegClass->getID() << "\n"); in handleSubReg()
180 TII->get(TII->getUndefInitOpcode(SubRegClass->getID())), in handleSubReg()
205 LLVM_DEBUG(dbgs() << "Register Class ID" << TargetRegClass->getID() << "\n"); in fixupIllOperand()
206 unsigned Opcode = TII->getUndefInitOpcode(TargetRegClass->getID()); in fixupIllOperand()
H A DRegisterBankInfo.cpp64 assert(RegBanks[Idx]->getID() == Idx && in RegisterBankInfo()
74 assert(Idx == RegBank.getID() && in verify()
271 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); in hashPartialMapping()
530 assert(RBI.getMaximumSize(RegBank->getID()) >= Length && in verify()
654 OS << "ID: " << getID() << " Cost: " << getCost() << " Mapping: "; in print()
794 OS << "Mapping ID: " << getInstrMapping().getID() << ' '; in print()
/freebsd/contrib/llvm-project/clang/lib/Frontend/
H A DTextDiagnosticPrinter.cpp58 if (Info.getID() == diag::fatal_too_many_errors) { in printDiagnosticOptions()
73 DiagnosticIDs::isBuiltinWarningOrExtension(Info.getID()) && in printDiagnosticOptions()
74 !DiagnosticIDs::isDefaultMappingAsError(Info.getID())) { in printDiagnosticOptions()
79 StringRef Opt = DiagnosticIDs::getWarningOptionForDiag(Info.getID()); in printDiagnosticOptions()
93 DiagnosticIDs::getCategoryNumberForDiag(Info.getID()); in printDiagnosticOptions()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp195 assert((RegBank->getID() == ARM::GPRRegBankID || in guessRegClass()
196 RegBank->getID() == ARM::FPRRegBankID) && in guessRegClass()
199 if (RegBank->getID() == ARM::FPRRegBankID) { in guessRegClass()
245 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
250 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
255 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
277 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
282 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
287 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectUnmergeValues()
520 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { in validReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp92 switch (RC->getID()) { in getCallerSavedRegs()
363 if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID()) in shouldCoalesce()
365 bool SmallSrc = SrcRC->getID() == Hexagon::HvxVRRegClass.getID(); in shouldCoalesce()
366 bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID(); in shouldCoalesce()
429 switch (RC.getID()) { in getHexagonSubRegIndex()
H A DHexagonMachineScheduler.cpp58 if (Q.getID() == TopQID && in SchedulingCost()
62 } else if (Q.getID() == BotQID && in SchedulingCost()
/freebsd/contrib/llvm-project/llvm/include/llvm/Option/
H A DOptSpecifier.h29 unsigned getID() const { return ID; } in getID() function
31 bool operator==(OptSpecifier Opt) const { return ID == Opt.getID(); }
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIMachineScheduler.cpp517 unsigned PredID = Pred->getID(); in addPred()
521 if (PredID == P->getID()) in addPred()
529 return PredID == S.first->getID(); in addPred()
536 unsigned SuccID = Succ->getID(); in addSucc()
540 if (SuccID == S.first->getID()) { in addSucc()
552 [=](SIScheduleBlock *P) { return SuccID == P->getID(); }) && in addSucc()
627 return CurrentBlocks[Node2CurrentBlock[SU->NodeNum]]->getID() == ID; in isSUInBlock()
1265 if (!--TopDownBlock2Index[Pred->getID()]) in topologicalSort()
1266 WorkList.push_back(Pred->getID()); in topologicalSort()
1275 assert(TopDownBlock2Index[i] > TopDownBlock2Index[Pred->getID()] && in topologicalSort()
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/freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/
H A DHLSL.cpp236 if (A->getOption().getID() == options::OPT_dxil_validator_version) { in TranslateArgs()
242 if (A->getOption().getID() == options::OPT_dxc_entrypoint) { in TranslateArgs()
248 if (A->getOption().getID() == options::OPT__SLASH_O) { in TranslateArgs()
260 if (A->getOption().getID() == options::OPT_emit_pristine_llvm) { in TranslateArgs()
268 if (A->getOption().getID() == options::OPT_dxc_hlsl_version) { in TranslateArgs()
/freebsd/contrib/llvm-project/llvm/lib/Option/
H A DOption.cpp101 if (getID() == Opt.getID()) in matches()
244 if (getID() == UnaliasedOption.getID()) in accept()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp173 if (RB.getID() == X86::GPRRegBankID) { in getRegClass()
183 if (RB.getID() == X86::VECRRegBankID) { in getRegClass()
198 if (RB.getID() == X86::PSRRegBankID) { in getRegClass()
290 if (DstSize > SrcSize && SrcRegBank.getID() == X86::GPRRegBankID && in selectCopy()
291 DstRegBank.getID() == X86::GPRRegBankID) { in selectCopy()
326 if (SrcRegBank.getID() == X86::GPRRegBankID && in selectCopy()
327 DstRegBank.getID() == X86::GPRRegBankID && SrcSize > DstSize && in selectCopy()
459 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
462 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
465 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp
/freebsd/contrib/llvm-project/lld/MachO/
H A DDriver.cpp74 switch (outputArg->getOption().getID()) { in getOutputType()
236 switch (arg->getOption().getID()) { in getLTOCachePolicy()
707 assert(arg->getOption().getID() == OPT_platform_version); in parsePlatformVersion()
865 if (arg->getOption().getID() == OPT_objc_stubs_small) { in getObjCStubsMode()
878 if (opt.getGroup().getID() == OPT_grp_deprecated) { in warnIfDeprecatedOption()
887 switch (opt.getGroup().getID()) { in warnIfUnimplementedOption()
1138 if (arg && arg->getOption().getID() == OPT_objc_relative_method_lists) in shouldEmitRelativeMethodLists()
1140 if (arg && arg->getOption().getID() == OPT_no_objc_relative_method_lists) in shouldEmitRelativeMethodLists()
1218 switch (opt.getID()) { in createFiles()
1255 addLibrary(arg->getValue(), opt.getID() == OPT_needed_l, in createFiles()
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/freebsd/contrib/llvm-project/clang/lib/ARCMigrate/
H A DTransProtectedScope.cpp120 if (I->getID() == diag::err_switch_into_protected_scope && in ProtectedScopeFixer()
133 assert(DiagI->getID() == diag::err_switch_into_protected_scope); in handleProtectedScopeError()
159 Pass.TA.clearDiagnostic(Diag.getID(), Diag.getLocation()); in handleProtectedNote()
/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DMemorySSA.h222 inline unsigned getID() const;
332 OptimizedID = DMA->getID();
340 return getDefiningAccess() && OptimizedID == getDefiningAccess()->getID();
395 OptimizedID = MA->getID();
403 return getOptimized() && OptimizedID == getOptimized()->getID();
413 unsigned getID() const { return ID; }
633 unsigned getID() const { return ID; }
662 inline unsigned MemoryAccess::getID() const {
666 return MD->getID();
667 return cast<MemoryPhi>(this)->getID();
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.cpp76 assert(getMaximumSize(RBGPR.getID()) == 128 && in AArch64RegisterBankInfo()
85 assert(getMaximumSize(RBFPR.getID()) == 512 && in AArch64RegisterBankInfo()
90 assert(getMaximumSize(RBCCR.getID()) == 32 && in AArch64RegisterBankInfo()
244 switch (RC.getID()) { in getRegBankFromRegClass()
415 assert((OpdMapper.getInstrMapping().getID() >= 1 && in applyMappingImpl()
416 OpdMapper.getInstrMapping().getID() <= 4) && in applyMappingImpl()
724 getCopyMapping(DstRB->getID(), SrcRB->getID(), Size), in getInstrMapping()
743 getCopyMapping(DstRB.getID(), SrcRB.getID(), Size), in getInstrMapping()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DStackMaps.h47 uint64_t getID() const { return MI->getOperand(IDPos).getImm(); } in getID() function
101 uint64_t getID() const { return getMetaOper(IDPos).getImm(); } in getID() function
204 uint64_t getID() const { return MI->getOperand(NumDefs + IDPos).getImm(); } in getID() function
H A DTargetRegisterInfo.h74 unsigned getID() const { return MC->getID(); } in getID() function
132 unsigned ID = RC->getID(); in hasSubClassEq()
801 return RCInfos[getNumRegClasses() * HwMode + RC.getID()]; in getRegClassInfo()
1357 bool isValid() const { return getID() != NumRegClasses; } in isValid()
1360 unsigned getID() const { return ID; } in getID() function
H A DRegisterBankInfo.h232 unsigned getID() const { return ID; } in getID() function
256 return getID() != InvalidMappingID && OperandsMapping; in isValid()
738 if (OpdMapper.getInstrMapping().getID() == DefaultMappingID) in applyMapping()
/freebsd/contrib/llvm-project/llvm/lib/DebugInfo/LogicalView/Core/
H A DLVReader.cpp71 return std::get<0>(l)->getID() < std::get<0>(r)->getID(); in checkIntegrityScopesTree()
84 Element->getID(), ElementName.c_str()); in checkIntegrityScopesTree()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCRegisterBankInfo.cpp36 switch (RC.getID()) { in getRegBankFromRegClass()
233 MappingID, Cost, getCopyMapping(DstRB.getID(), SrcRB.getID(), DstSize), in getInstrMapping()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DDAGISelEmitter.cpp129 return LHS->getID() < RHS->getID(); in operator ()()

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