| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.cpp | 80 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
84 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb1InstrInfo.cpp | 110 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
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| H A D | ThumbRegisterInfo.cpp | 76 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
95 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
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| H A D | ARMLoadStoreOptimizer.cpp | 812 MIB.addReg(Base, getDefRegState(true)) in CreateLoadStoreMulti()
828 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second)); in CreateLoadStoreMulti()
1351 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLSMultiple()
1532 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLoadStore()
1536 .addReg(MO.getReg(), (isLd ? getDefRegState(true) in MergeBaseUpdateLoadStore()
1743 .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill)) in InsertLDR_STR()
1814 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill)) in FixInvalidRegPairOp()
1815 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill)) in FixInvalidRegPairOp()
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| H A D | MLxExpansionPass.cpp | 298 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead)); in ExpandFPMLxInstruction()
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| H A D | ARMBaseRegisterInfo.cpp | 508 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
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| H A D | Thumb1FrameLowering.cpp | 1074 MIB.addReg(Reg, getDefRegState(true)); in popRegsFromStack()
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| H A D | ARMFrameLowering.cpp | 1676 MIB.addReg(Reg, getDefRegState(true)); in emitPopInst()
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| H A D | ARMExpandPseudoInsts.cpp | 884 getDefRegState(MI.getOperand(0).isDef()); in ExpandMQQPRLoadStore()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 549 inline unsigned getDefRegState(bool B) { in getDefRegState() function
577 return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) | in getRegState()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64LowerHomogeneousPrologEpilog.cpp | 276 MIB.addReg(Reg2, getDefRegState(true)); in emitLoad()
277 MIB.addReg(Reg1, getDefRegState(true)) in emitLoad()
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| H A D | AArch64FrameLowering.cpp | 3505 getDefRegState(true)); in restoreCalleeSavedRegisters()
3522 MIB.addReg(Reg2, getDefRegState(true)); in restoreCalleeSavedRegisters()
3527 MIB.addReg(Reg1, getDefRegState(true)); in restoreCalleeSavedRegisters()
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| H A D | AArch64InstrInfo.cpp | 5140 .addReg(DestReg, getDefRegState(true)) in loadRegFromStackSlot()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiMemAluCombiner.cpp | 259 InstrBuilder.addReg(Dest.getReg(), getDefRegState(true)); in insertMergedInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineInstrBundle.cpp | 214 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) | in finalizeBundle()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 1128 .addReg(Tmp, getDefRegState(true)) in fixSCCCopies()
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| H A D | SIRegisterInfo.cpp | 1548 unsigned SrcDstRegState = getDefRegState(!IsStore); in buildSpillLoadStore()
1645 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill)); in buildSpillLoadStore()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 391 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 322 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)) in emitSPUpdate()
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| H A D | X86InstrInfo.cpp | 8439 MIB.addReg(ImpOp.getReg(), getDefRegState(ImpOp.isDef()) | in unfoldMemoryOperand()
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