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Searched refs:getCondCode (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp324 static MSP430CC::CondCodes getCondCode(unsigned Cond) { in getCondCode() function
353 MI.addOperand(MCOperand::createImm(getCondCode(Cond))); in getInstructionCJ()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp749 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_UINT()
759 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_SINT()
837 CC = DAG.getCondCode(InverseCC); in LowerSELECT_CC()
843 CC = DAG.getCondCode(SwapInvCC); in LowerSELECT_CC()
871 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
879 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
911 DAG.getCondCode(CCOpcode)); in LowerSELECT_CC()
937 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
H A DSIISelLowering.cpp6041 DAG.getCondCode(CCOpcode)); in lowerICMPIntrinsic()
6070 Src1, DAG.getCondCode(CCOpcode)); in lowerFCMPIntrinsic()
6110 DAG.getConstant(0, SL, MVT::i32), DAG.getCondCode(ISD::SETNE)); in lowerBALLOTIntrinsic()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h828 SDValue getCondCode(ISD::CondCode Cond);
1242 {VT, MVT::Other}, {Chain, LHS, RHS, getCondCode(Cond)});
1243 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
1254 return getNode(ISD::VP_SETCC, DL, VT, LHS, RHS, getCondCode(Cond), Mask,
1273 False, getCondCode(Cond));
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp1111 DAG.getCondCode(CCCode), NewLHS, NewRHS, in SoftenFloatOp_BR_CC()
1196 DAG.getCondCode(CCCode)), in SoftenFloatOp_SELECT_CC()
1218 NewRHS, DAG.getCondCode(CCCode)); in SoftenFloatOp_SETCC()
1221 DAG.getCondCode(CCCode)), 0); in SoftenFloatOp_SETCC()
2164 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandFloatOp_BR_CC()
2249 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SELECT_CC()
H A DLegalizeIntegerTypes.cpp5390 LHSHi, RHSHi, DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
5447 DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
5476 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandIntOp_BR_CC()
5495 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SELECT_CC()
5512 DAG.UpdateNodeOperands(N, NewLHS, NewRHS, DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SETCC()
H A DLegalizeDAG.cpp4088 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
4234 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
4266 Tmp4 = DAG.getCondCode(NeedInvert ? ISD::SETEQ : ISD::SETNE); in ExpandNode()
H A DTargetLowering.cpp9191 DAG.getCondCode(ISD::SETNE), Mask, EVL); in expandVPCTTZElements()
10291 {Op0, Op1, DAG.getCondCode(CC)})) { in expandIntMINMAX()
10298 {Op0, Op1, DAG.getCondCode(CC)})) { in expandIntMINMAX()
11557 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
11570 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
H A DSelectionDAGBuilder.cpp8225 Opers.push_back(DAG.getCondCode(Condition)); in visitConstrainedFPIntrinsic()
H A DSelectionDAG.cpp2017 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { in getCondCode() function in SelectionDAG
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2978 {Src, Src, DAG.getCondCode(ISD::SETNE), in lowerFP_TO_INT_SAT()
3088 {Abs, MaxValSplat, DAG.getCondCode(ISD::SETOLT), in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
3170 {Chain, Src, Src, DAG.getCondCode(ISD::SETUNE), in lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND()
3197 {Abs, MaxValSplat, DAG.getCondCode(ISD::SETOLT), Mask, Mask, VL}); in lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND()
5540 {Source, AllZero, DAG.getCondCode(ISD::SETNE), in lowerVPCttzElements()
5833 {FPCLASS, TDCMaskV, DAG.getCondCode(ISD::SETEQ), in LowerIS_FPCLASS()
5845 {AND, SplatZero, DAG.getCondCode(ISD::SETNE), in LowerIS_FPCLASS()
5917 {X, X, DAG.getCondCode(ISD::SETOEQ), in lowerFMAXIMUM_FMINIMUM()
5926 {Y, Y, DAG.getCondCode(ISD::SETOEQ), in lowerFMAXIMUM_FMINIMUM()
7805 SDValue SetNE = DAG.getCondCode(ISD::SETNE); in lowerSELECT()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp983 ARMCC::CondCodes getCondCode() const { in getCondCode() function in __anon6be9c9a00111::ARMOperand
2464 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeNoAL()
2471 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedI()
2478 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedS()
2486 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedU()
2493 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedFP()
2534 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
2535 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
2586 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands()
2591 Inst.addOperand(MCOperand::createImm(unsigned(ARMCC::getOppositeCondition(getCondCode())))); in addITCondCodeInvOperands()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp631 AArch64CC::CondCode getCondCode() const { in getCondCode() function in __anon730428320111::AArch64Operand
1958 Inst.addOperand(MCOperand::createImm(getCondCode())); in addCondCodeOperands()
2562 OS << "<condcode " << getCondCode() << ">"; in print()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp21048 N->getOperand(2), Splat, DAG.getCondCode(CC)); in tryConvertSVEWideCompare()
21451 N->getOperand(3), DAG.getCondCode(ISD::SETUGE)); in performIntrinsicCombine()
21457 N->getOperand(3), DAG.getCondCode(ISD::SETUGT)); in performIntrinsicCombine()
21463 N->getOperand(3), DAG.getCondCode(ISD::SETGE)); in performIntrinsicCombine()
21469 N->getOperand(3), DAG.getCondCode(ISD::SETGT)); in performIntrinsicCombine()
21475 N->getOperand(3), DAG.getCondCode(ISD::SETEQ)); in performIntrinsicCombine()
21481 N->getOperand(3), DAG.getCondCode(ISD::SETNE)); in performIntrinsicCombine()
21486 N->getOperand(3), DAG.getCondCode(ISD::SETUO)); in performIntrinsicCombine()
24217 SetCC.getOperand(2) == DAG.getCondCode(ISD::SETGT)) { in performVSelectCombine()
27277 {Pg, Op1, Op2, DAG.getCondCode(ISD::SETNE)}); in convertFixedMaskToScalableVector()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp6820 DAG.getCondCode(ISD::SETEQ)); in LowerVSETCC()
9317 DAG.getCondCode(ISD::SETNE)); in LowerTruncatei1()
10532 DAG.getCondCode(CC)); in LowerFSETCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp3744 DAG.getCondCode(CC)); in LowerSETCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp23115 SDValue CC = DAG.getCondCode(Cond); in splitIntVSETCC()