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Searched refs:getCondCode (Results 1 – 20 of 20) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp325 static MSP430CC::CondCodes getCondCode(unsigned Cond) { in getCondCode() function
354 MI.addOperand(MCOperand::createImm(getCondCode(Cond))); in getInstructionCJ()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp753 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_UINT()
763 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_SINT()
841 CC = DAG.getCondCode(InverseCC); in LowerSELECT_CC()
847 CC = DAG.getCondCode(SwapInvCC); in LowerSELECT_CC()
875 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
883 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
915 DAG.getCondCode(CCOpcode)); in LowerSELECT_CC()
941 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
H A DSIISelLowering.cpp6385 DAG.getCondCode(CCOpcode)); in lowerICMPIntrinsic()
6414 DAG.getCondCode(CCOpcode)); in lowerFCMPIntrinsic()
6454 DAG.getConstant(0, SL, MVT::i32), DAG.getCondCode(ISD::SETNE)); in lowerBALLOTIntrinsic()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h860 LLVM_ABI SDValue getCondCode(ISD::CondCode Cond);
1320 {VT, MVT::Other}, {Chain, LHS, RHS, getCondCode(Cond)});
1321 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
1332 return getNode(ISD::VP_SETCC, DL, VT, LHS, RHS, getCondCode(Cond), Mask,
1351 False, getCondCode(Cond));
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp3137 {Src, Src, DAG.getCondCode(ISD::SETNE), in lowerFP_TO_INT_SAT()
3300 {Abs, MaxValSplat, DAG.getCondCode(ISD::SETOLT), in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
3380 {Chain, Src, Src, DAG.getCondCode(ISD::SETUNE), in lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND()
3407 {Abs, MaxValSplat, DAG.getCondCode(ISD::SETOLT), Mask, Mask, VL}); in lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND()
6495 {Source, AllZero, DAG.getCondCode(ISD::SETNE), in lowerVPCttzElements()
6757 {FPCLASS, TDCMaskV, DAG.getCondCode(ISD::SETEQ), in LowerIS_FPCLASS()
6769 {AND, SplatZero, DAG.getCondCode(ISD::SETNE), in LowerIS_FPCLASS()
6841 {X, X, DAG.getCondCode(ISD::SETOEQ), in lowerFMAXIMUM_FMINIMUM()
6850 {Y, Y, DAG.getCondCode(ISD::SETOEQ), in lowerFMAXIMUM_FMINIMUM()
9264 SDValue SetNE = DAG.getCondCode(ISD::SETNE); in lowerSELECT()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp1256 DAG.getCondCode(CCCode), NewLHS, NewRHS, in SoftenFloatOp_BR_CC()
1341 DAG.getCondCode(CCCode)), in SoftenFloatOp_SELECT_CC()
1363 NewRHS, DAG.getCondCode(CCCode)); in SoftenFloatOp_SETCC()
1366 DAG.getCondCode(CCCode)), 0); in SoftenFloatOp_SETCC()
2380 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandFloatOp_BR_CC()
2465 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SELECT_CC()
H A DLegalizeIntegerTypes.cpp5629 LHSHi, RHSHi, DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
5686 DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
5715 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandIntOp_BR_CC()
5734 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SELECT_CC()
5751 DAG.UpdateNodeOperands(N, NewLHS, NewRHS, DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SETCC()
H A DLegalizeDAG.cpp4226 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
4372 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
4404 Tmp4 = DAG.getCondCode(NeedInvert ? ISD::SETEQ : ISD::SETNE); in ExpandNode()
H A DTargetLowering.cpp9597 DAG.getCondCode(ISD::SETNE), Mask, EVL); in expandVPCTTZElements()
10783 {Op0, Op1, DAG.getCondCode(CC)})) { in expandIntMINMAX()
10790 {Op0, Op1, DAG.getCondCode(CC)})) { in expandIntMINMAX()
12098 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
12111 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
H A DSelectionDAGBuilder.cpp8381 Opers.push_back(DAG.getCondCode(Condition)); in visitConstrainedFPIntrinsic()
H A DSelectionDAG.cpp2074 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { in getCondCode() function in SelectionDAG
H A DDAGCombiner.cpp13107 Cond.getOperand(2) == DAG.getCondCode(ISD::SETGT) && in combineVSelectWithAllOnesOrZeros()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp983 ARMCC::CondCodes getCondCode() const { in getCondCode() function in __anon6be9c9a00111::ARMOperand
2465 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeNoAL()
2472 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedI()
2479 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedS()
2487 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedU()
2494 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedFP()
2535 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
2536 unsigned RegNum = getCondCode() == ARMCC::AL ? ARM::NoRegister : ARM::CPSR; in addCondCodeOperands()
2587 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands()
2592 Inst.addOperand(MCOperand::createImm(unsigned(ARMCC::getOppositeCondition(getCondCode())))); in addITCondCodeInvOperands()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp647 AArch64CC::CondCode getCondCode() const { in getCondCode() function in __anon730428320111::AArch64Operand
1987 Inst.addOperand(MCOperand::createImm(getCondCode())); in addCondCodeOperands()
2620 OS << "<condcode " << getCondCode() << ">"; in print()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp797 SDValue SetNE = DAG.getCondCode(ISD::SETNE); in lowerSELECT()
848 SDValue TargetCC = DAG.getCondCode(CCVal); in lowerSELECT()
854 TargetCC = DAG.getCondCode(ISD::getSetCCInverse(CCVal, LHS.getValueType())); in lowerSELECT()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp21791 N->getOperand(2), Splat, DAG.getCondCode(CC)); in tryConvertSVEWideCompare()
22315 N->getOperand(3), DAG.getCondCode(ISD::SETUGE)); in performIntrinsicCombine()
22321 N->getOperand(3), DAG.getCondCode(ISD::SETUGT)); in performIntrinsicCombine()
22327 N->getOperand(3), DAG.getCondCode(ISD::SETGE)); in performIntrinsicCombine()
22333 N->getOperand(3), DAG.getCondCode(ISD::SETGT)); in performIntrinsicCombine()
22339 N->getOperand(3), DAG.getCondCode(ISD::SETEQ)); in performIntrinsicCombine()
22345 N->getOperand(3), DAG.getCondCode(ISD::SETNE)); in performIntrinsicCombine()
22350 N->getOperand(3), DAG.getCondCode(ISD::SETUO)); in performIntrinsicCombine()
25626 SetCC.getOperand(2) == DAG.getCondCode(ISD::SETGT)) { in performVSelectCombine()
28894 {Pg, Op1, Op2, DAG.getCondCode(CC)}); in convertFixedMaskToScalableVector()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp6886 DAG.getCondCode(ISD::SETEQ)); in LowerVSETCC()
9369 DAG.getCondCode(ISD::SETNE)); in LowerTruncatei1()
10590 DAG.getCondCode(CC)); in LowerFSETCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp3759 DAG.getCondCode(CC)); in LowerSETCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp23855 SDValue CC = DAG.getCondCode(Cond); in splitVSETCC()
/freebsd/contrib/llvm-project/llvm/include/llvm/Testing/Demangle/
H A DDemangleTestCases.inc15061 {"_ZN4llvm12SelectionDAG11getCondCodeENS_3ISD8CondCodeE", "llvm::SelectionDAG::getCondCode(llvm::IS…