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Searched refs:getBaseRegister (Results 1 – 25 of 27) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/
H A DSFrame.h134 BaseReg getBaseRegister() const { return static_cast<BaseReg>(Info & 1); }
136 setFREInfo(RA, getOffsetSize(), getOffsetCount(), getBaseRegister());
140 getBaseRegister());
143 setFREInfo(isReturnAddressSigned(), getOffsetSize(), N, getBaseRegister());
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.cpp154 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister())) in getReservedRegs()
159 setBitVector(getBaseRegister()); in getReservedRegs()
185 BasePtr = (FIndex < 0 ? FramePtr : getBaseRegister()); in eliminateFrameIndex()
H A DM68kRegisterInfo.h109 unsigned getBaseRegister() const { return BasePtr; } in getBaseRegister() function
H A DM68kFrameLowering.cpp86 FrameReg = TRI->getBaseRegister(); in getFrameIndexReference()
487 unsigned BasePtr = TRI->getBaseRegister(); in emitPrologue()
797 SavedRegs.set(TRI->getBaseRegister()); in determineCalleeSaves()
H A DM68kCollapseMOVEMPass.cpp223 Reg == TRI->getBaseRegister() || in ProcessMI()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.cpp57 Reserved.set(getBaseRegister()); in getReservedRegs()
153 FrameReg = getBaseRegister(); in eliminateFrameIndex()
260 Register LanaiRegisterInfo::getBaseRegister() const { return Lanai::R14; } in getBaseRegister() function in LanaiRegisterInfo
H A DLanaiRegisterInfo.h44 Register getBaseRegister() const;
H A DLanaiFrameLowering.cpp208 SavedRegs.reset(LRI->getBaseRegister()); in determineCalleeSaves()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.h165 Register getBaseRegister() const { return BasePtr; } in getBaseRegister() function
H A DX86ArgumentStackSlotRebase.cpp120 Register BasePtr = TRI->getBaseRegister(); in runOnMachineFunction()
H A DX86FrameLowering.cpp1616 Register BasePtr = TRI->getBaseRegister(); in emitPrologue()
2671 FrameReg = IsFixed ? TRI->getFramePtr() : TRI->getBaseRegister(); in getFrameIndexReference()
3073 Register BaseReg = this->TRI->getBaseRegister(); in spillCalleeSavedRegisters()
3177 Register BaseReg = this->TRI->getBaseRegister(); in restoreCalleeSavedRegisters()
3209 Register BasePtr = TRI->getBaseRegister(); in determineCalleeSaves()
3976 Register BasePtr = TRI->getBaseRegister(); in restoreWin32EHStackPointers()
4436 BP = TRI->getBaseRegister(); in saveAndRestoreFPBPUsingSP()
4559 BP = TRI->getBaseRegister(); in spillFPBP()
H A DX86SelectionDAGInfo.cpp70 return llvm::is_contained(ClobberSet, TRI->getBaseRegister()); in isBaseRegConflictPossible()
H A DX86RegisterInfo.cpp583 Register BasePtr = getX86SubSuperRegister(getBaseRegister(), 64); in getReservedRegs()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h131 Register getBaseRegister() const { return BasePtr; } in getBaseRegister() function
H A DARMFrameLowering.cpp1376 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), RegInfo->getBaseRegister()) in emitPrologue()
1381 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), RegInfo->getBaseRegister()) in emitPrologue()
1597 FrameReg = RegInfo->getBaseRegister(); in ResolveFrameIndexReference()
1645 FrameReg = RegInfo->getBaseRegister(); in ResolveFrameIndexReference()
2602 SavedRegs.set(RegInfo->getBaseRegister()); in determineCalleeSaves()
H A DThumb1FrameLowering.cpp168 Register BasePtr = RegInfo->getBaseRegister(); in emitPrologue()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.h128 unsigned getBaseRegister() const;
H A DAArch64RegisterInfo.cpp625 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; } in getBaseRegister() function in AArch64RegisterInfo
1314 return getBaseRegister(); in getLocalAddressRegister()
H A DAArch64FrameLowering.cpp2397 TII->copyPhysReg(MBB, MBBI, DL, RegInfo->getBaseRegister(), AArch64::SP, in emitPrologue()
3060 FrameReg = RegInfo->hasBasePointer(MF) ? RegInfo->getBaseRegister() in resolveFrameOffsetReference()
3096 FrameReg = RegInfo->getBaseRegister(); in resolveFrameOffsetReference()
3941 ? RegInfo->getBaseRegister() in determineCalleeSaves()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.h186 Register getBaseRegister(const MachineFunction &MF) const;
H A DPPCFrameLowering.cpp396 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg; in replaceFPWithRealFP()
653 Register BPReg = RegInfo->getBaseRegister(MF); in emitPrologue()
1268 Register BPReg = RegInfo->getBaseRegister(MF); in inlineStackProbe()
1575 Register BPReg = RegInfo->getBaseRegister(MF); in emitEpilogue()
2032 SavedRegs.reset(RegInfo->getBaseRegister(MF)); in determineCalleeSaves()
2038 (RegInfo->getBaseRegister(MF) == (isPPC64 ? PPC::X30 : PPC::R30)) && in determineCalleeSaves()
2207 Register BP = RegInfo->getBaseRegister(MF); in processFunctionBeforeFrameFinalized()
H A DPPCRegisterInfo.cpp1783 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false); in eliminateFrameIndex()
1935 Register PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const { in getBaseRegister() function in PPCRegisterInfo
2005 return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset); in needsFrameBaseReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h136 Register getBaseRegister() const;
H A DSIFrameLowering.cpp1139 TRI.hasBasePointer(MF) ? TRI.getBaseRegister() : Register(); in emitPrologue()
1309 .addReg(TRI.getBaseRegister()) in emitEpilogue()
1602 Register BasePtrReg = TRI->getBaseRegister(); in determinePrologEpilogSGPRSaves()
1853 Register BasePtrReg = RI->getBaseRegister(); in assignCalleeSavedSpillSlots()
H A DSIRegisterInfo.cpp532 Register SIRegisterInfo::getBaseRegister() const { return AMDGPU::SGPR34; } in getBaseRegister() function in SIRegisterInfo
730 MCRegister BasePtrReg = getBaseRegister(); in getReservedRegs()
2005 ? getBaseRegister() in buildVGPRSpillLoadStore()
2373 ? getBaseRegister() in eliminateFrameIndex()

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