1 /*- 2 * Broadcom NetXtreme-C/E network driver. 3 * 4 * Copyright (c) 2016 Broadcom, All Rights Reserved. 5 * The term Broadcom refers to Broadcom Limited and/or its subsidiaries 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #ifndef _BNXT_H 31 #define _BNXT_H 32 33 #include <sys/param.h> 34 #include <sys/socket.h> 35 #include <sys/sysctl.h> 36 #include <sys/taskqueue.h> 37 #include <sys/bitstring.h> 38 39 #include <machine/bus.h> 40 41 #include <net/ethernet.h> 42 #include <net/if.h> 43 #include <net/if_var.h> 44 #include <net/iflib.h> 45 #include <linux/types.h> 46 47 #include "hsi_struct_def.h" 48 #include "bnxt_dcb.h" 49 #include "bnxt_auxbus_compat.h" 50 51 #define DFLT_HWRM_CMD_TIMEOUT 500 52 53 /* PCI IDs */ 54 #define BROADCOM_VENDOR_ID 0x14E4 55 56 #define BCM57301 0x16c8 57 #define BCM57302 0x16c9 58 #define BCM57304 0x16ca 59 #define BCM57311 0x16ce 60 #define BCM57312 0x16cf 61 #define BCM57314 0x16df 62 #define BCM57402 0x16d0 63 #define BCM57402_NPAR 0x16d4 64 #define BCM57404 0x16d1 65 #define BCM57404_NPAR 0x16e7 66 #define BCM57406 0x16d2 67 #define BCM57406_NPAR 0x16e8 68 #define BCM57407 0x16d5 69 #define BCM57407_NPAR 0x16ea 70 #define BCM57407_SFP 0x16e9 71 #define BCM57412 0x16d6 72 #define BCM57412_NPAR1 0x16de 73 #define BCM57412_NPAR2 0x16eb 74 #define BCM57414 0x16d7 75 #define BCM57414_NPAR1 0x16ec 76 #define BCM57414_NPAR2 0x16ed 77 #define BCM57416 0x16d8 78 #define BCM57416_NPAR1 0x16ee 79 #define BCM57416_NPAR2 0x16ef 80 #define BCM57416_SFP 0x16e3 81 #define BCM57417 0x16d9 82 #define BCM57417_NPAR1 0x16c0 83 #define BCM57417_NPAR2 0x16cc 84 #define BCM57417_SFP 0x16e2 85 #define BCM57454 0x1614 86 #define BCM58700 0x16cd 87 #define BCM57508 0x1750 88 #define BCM57504 0x1751 89 #define BCM57504_NPAR 0x1801 90 #define BCM57502 0x1752 91 #define BCM57608 0x1760 92 #define BCM57604 0x1761 93 #define BCM57602 0x1762 94 #define BCM57601 0x1763 95 #define NETXTREME_C_VF1 0x16cb 96 #define NETXTREME_C_VF2 0x16e1 97 #define NETXTREME_C_VF3 0x16e5 98 #define NETXTREME_E_VF1 0x16c1 99 #define NETXTREME_E_VF2 0x16d3 100 #define NETXTREME_E_VF3 0x16dc 101 102 #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \ 103 (((data1) & \ 104 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\ 105 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL) 106 107 #define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \ 108 (((data1) & \ 109 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >> \ 110 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT) 111 112 #define BNXT_EVENT_INVALID_SIGNAL_DATA(data2) \ 113 (((data2) & \ 114 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >> \ 115 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT) 116 117 #define BNXT_EVENT_DBR_EPOCH(data) \ 118 (((data) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK) >> \ 119 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT) 120 121 #define BNXT_EVENT_THERMAL_THRESHOLD_TEMP(data2) \ 122 (((data2) & \ 123 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK) >> \ 124 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_SFT) 125 126 #define EVENT_DATA2_NVM_ERR_ADDR(data2) \ 127 (((data2) & \ 128 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK) >> \ 129 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT) 130 131 #define EVENT_DATA1_THERMAL_THRESHOLD_DIR_INCREASING(data1) \ 132 (((data1) & \ 133 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR) == \ 134 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING) 135 136 #define EVENT_DATA1_NVM_ERR_TYPE_WRITE(data1) \ 137 (((data1) & \ 138 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK) == \ 139 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE) 140 141 #define EVENT_DATA1_NVM_ERR_TYPE_ERASE(data1) \ 142 (((data1) & \ 143 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK) == \ 144 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE) 145 146 #define EVENT_DATA1_THERMAL_THRESHOLD_TYPE(data1) \ 147 ((data1) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK) 148 149 #define BNXT_EVENT_THERMAL_CURRENT_TEMP(data2) \ 150 ((data2) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK) 151 152 #define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1) \ 153 (((data1) & \ 154 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\ 155 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION) 156 157 #define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2) \ 158 ((data2) & \ 159 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK) 160 161 #define EVENT_DATA1_RECOVERY_ENABLED(data1) \ 162 !!((data1) & \ 163 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED) 164 165 #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \ 166 !!((data1) & \ 167 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC) 168 169 #define INVALID_STATS_CTX_ID -1 170 171 /* Maximum numbers of RX and TX descriptors. iflib requires this to be a power 172 * of two. The hardware has no particular limitation. */ 173 #define BNXT_MAX_RXD ((INT32_MAX >> 1) + 1) 174 #define BNXT_MAX_TXD ((INT32_MAX >> 1) + 1) 175 176 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 177 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 178 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 179 180 #define BNXT_MAX_MTU 9600 181 182 #define BNXT_RSS_HASH_TYPE_TCPV4 0 183 #define BNXT_RSS_HASH_TYPE_UDPV4 1 184 #define BNXT_RSS_HASH_TYPE_IPV4 2 185 #define BNXT_RSS_HASH_TYPE_TCPV6 3 186 #define BNXT_RSS_HASH_TYPE_UDPV6 4 187 #define BNXT_RSS_HASH_TYPE_IPV6 5 188 #define BNXT_GET_RSS_PROFILE_ID(rss_hash_type) ((rss_hash_type >> 1) & 0x1F) 189 190 #define BNXT_NO_MORE_WOL_FILTERS 0xFFFF 191 #define bnxt_wol_supported(softc) (!((softc)->flags & BNXT_FLAG_VF) && \ 192 ((softc)->flags & BNXT_FLAG_WOL_CAP )) 193 /* 64-bit doorbell */ 194 #define DBR_INDEX_MASK 0x0000000000ffffffULL 195 #define DBR_PI_LO_MASK 0xff000000UL 196 #define DBR_PI_LO_SFT 24 197 #define DBR_EPOCH_MASK 0x01000000UL 198 #define DBR_EPOCH_SFT 24 199 #define DBR_TOGGLE_MASK 0x06000000UL 200 #define DBR_TOGGLE_SFT 25 201 #define DBR_XID_MASK 0x000fffff00000000ULL 202 #define DBR_XID_SFT 32 203 #define DBR_PI_HI_MASK 0xf0000000000000ULL 204 #define DBR_PI_HI_SFT 52 205 #define DBR_PATH_L2 (0x1ULL << 56) 206 #define DBR_VALID (0x1ULL << 58) 207 #define DBR_TYPE_SQ (0x0ULL << 60) 208 #define DBR_TYPE_RQ (0x1ULL << 60) 209 #define DBR_TYPE_SRQ (0x2ULL << 60) 210 #define DBR_TYPE_SRQ_ARM (0x3ULL << 60) 211 #define DBR_TYPE_CQ (0x4ULL << 60) 212 #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60) 213 #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60) 214 #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60) 215 #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60) 216 #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60) 217 #define DBR_TYPE_NQ (0xaULL << 60) 218 #define DBR_TYPE_NQ_ARM (0xbULL << 60) 219 #define DBR_TYPE_PUSH_START (0xcULL << 60) 220 #define DBR_TYPE_PUSH_END (0xdULL << 60) 221 #define DBR_TYPE_NQ_MASK (0xeULL << 60) 222 #define DBR_TYPE_NULL (0xfULL << 60) 223 224 #define BNXT_MAX_L2_QUEUES 128 225 #define BNXT_ROCE_IRQ_COUNT 9 226 227 #define BNXT_MAX_NUM_QUEUES (BNXT_MAX_L2_QUEUES + BNXT_ROCE_IRQ_COUNT) 228 229 /* Completion related defines */ 230 #define CMP_VALID(cmp, v_bit) \ 231 ((!!(((struct cmpl_base *)(cmp))->info3_v & htole32(CMPL_BASE_V))) == !!(v_bit) ) 232 233 /* Chip class phase 5 */ 234 #define BNXT_CHIP_P5(sc) ((sc->flags & BNXT_FLAG_CHIP_P5)) 235 236 /* Chip class phase 7 */ 237 #define BNXT_CHIP_P7(sc) ((sc->flags & BNXT_FLAG_CHIP_P7)) 238 239 /* Chip class phase 5 plus */ 240 #define BNXT_CHIP_P5_PLUS(sc) \ 241 (BNXT_CHIP_P5(sc) || BNXT_CHIP_P7(sc)) 242 243 #define DB_PF_OFFSET_P5 0x10000 244 #define DB_VF_OFFSET_P5 0x4000 245 #define NQ_VALID(cmp, v_bit) \ 246 ((!!(((nq_cn_t *)(cmp))->v & htole32(NQ_CN_V))) == !!(v_bit) ) 247 248 #ifndef DIV_ROUND_UP 249 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 250 #endif 251 #ifndef roundup 252 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 253 #endif 254 255 #define NEXT_CP_CONS_V(ring, cons, v_bit) do { \ 256 if (__predict_false(++(cons) == (ring)->ring_size)) \ 257 ((cons) = 0, (v_bit) = !v_bit); \ 258 } while (0) 259 260 #define RING_NEXT(ring, idx) (__predict_false(idx + 1 == (ring)->ring_size) ? \ 261 0 : idx + 1) 262 263 #define CMPL_PREFETCH_NEXT(cpr, idx) \ 264 __builtin_prefetch(&((struct cmpl_base *)(cpr)->ring.vaddr)[((idx) +\ 265 (CACHE_LINE_SIZE / sizeof(struct cmpl_base))) & \ 266 ((cpr)->ring.ring_size - 1)]) 267 268 /* Lock macros */ 269 #define BNXT_HWRM_LOCK_INIT(_softc, _name) \ 270 mtx_init(&(_softc)->hwrm_lock, _name, "BNXT HWRM Lock", MTX_DEF) 271 #define BNXT_HWRM_LOCK(_softc) mtx_lock(&(_softc)->hwrm_lock) 272 #define BNXT_HWRM_UNLOCK(_softc) mtx_unlock(&(_softc)->hwrm_lock) 273 #define BNXT_HWRM_LOCK_DESTROY(_softc) mtx_destroy(&(_softc)->hwrm_lock) 274 #define BNXT_HWRM_LOCK_ASSERT(_softc) mtx_assert(&(_softc)->hwrm_lock, \ 275 MA_OWNED) 276 #define BNXT_IS_FLOW_CTRL_CHANGED(link_info) \ 277 ((link_info->last_flow_ctrl.tx != link_info->flow_ctrl.tx) || \ 278 (link_info->last_flow_ctrl.rx != link_info->flow_ctrl.rx) || \ 279 (link_info->last_flow_ctrl.autoneg != link_info->flow_ctrl.autoneg)) 280 281 /* Chip info */ 282 #define BNXT_TSO_SIZE UINT16_MAX 283 284 #define min_t(type, x, y) ({ \ 285 type __min1 = (x); \ 286 type __min2 = (y); \ 287 __min1 < __min2 ? __min1 : __min2; }) 288 289 #define max_t(type, x, y) ({ \ 290 type __max1 = (x); \ 291 type __max2 = (y); \ 292 __max1 > __max2 ? __max1 : __max2; }) 293 294 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 295 296 #define BNXT_IFMEDIA_ADD(supported, fw_speed, ifm_speed) do { \ 297 if ((supported) & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_ ## fw_speed) \ 298 ifmedia_add(softc->media, IFM_ETHER | (ifm_speed), 0, NULL); \ 299 } while(0) 300 301 #define BNXT_MIN_FRAME_SIZE 52 /* Frames must be padded to this size for some A0 chips */ 302 303 #define BNXT_RX_STATS_EXT_OFFSET(counter) \ 304 (offsetof(struct rx_port_stats_ext, counter) / 8) 305 306 #define BNXT_RX_STATS_EXT_NUM_LEGACY \ 307 BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks) 308 309 #define BNXT_TX_STATS_EXT_OFFSET(counter) \ 310 (offsetof(struct tx_port_stats_ext, counter) / 8) 311 312 extern const char bnxt_driver_version[]; 313 typedef void (*bnxt_doorbell_tx)(void *, uint16_t idx); 314 typedef void (*bnxt_doorbell_rx)(void *, uint16_t idx); 315 typedef void (*bnxt_doorbell_rx_cq)(void *, bool); 316 typedef void (*bnxt_doorbell_tx_cq)(void *, bool); 317 typedef void (*bnxt_doorbell_nq)(void *, bool); 318 319 typedef struct bnxt_doorbell_ops { 320 bnxt_doorbell_tx bnxt_db_tx; 321 bnxt_doorbell_rx bnxt_db_rx; 322 bnxt_doorbell_rx_cq bnxt_db_rx_cq; 323 bnxt_doorbell_tx_cq bnxt_db_tx_cq; 324 bnxt_doorbell_nq bnxt_db_nq; 325 } bnxt_dooorbell_ops_t; 326 /* NVRAM access */ 327 enum bnxt_nvm_directory_type { 328 BNX_DIR_TYPE_UNUSED = 0, 329 BNX_DIR_TYPE_PKG_LOG = 1, 330 BNX_DIR_TYPE_UPDATE = 2, 331 BNX_DIR_TYPE_CHIMP_PATCH = 3, 332 BNX_DIR_TYPE_BOOTCODE = 4, 333 BNX_DIR_TYPE_VPD = 5, 334 BNX_DIR_TYPE_EXP_ROM_MBA = 6, 335 BNX_DIR_TYPE_AVS = 7, 336 BNX_DIR_TYPE_PCIE = 8, 337 BNX_DIR_TYPE_PORT_MACRO = 9, 338 BNX_DIR_TYPE_APE_FW = 10, 339 BNX_DIR_TYPE_APE_PATCH = 11, 340 BNX_DIR_TYPE_KONG_FW = 12, 341 BNX_DIR_TYPE_KONG_PATCH = 13, 342 BNX_DIR_TYPE_BONO_FW = 14, 343 BNX_DIR_TYPE_BONO_PATCH = 15, 344 BNX_DIR_TYPE_TANG_FW = 16, 345 BNX_DIR_TYPE_TANG_PATCH = 17, 346 BNX_DIR_TYPE_BOOTCODE_2 = 18, 347 BNX_DIR_TYPE_CCM = 19, 348 BNX_DIR_TYPE_PCI_CFG = 20, 349 BNX_DIR_TYPE_TSCF_UCODE = 21, 350 BNX_DIR_TYPE_ISCSI_BOOT = 22, 351 BNX_DIR_TYPE_ISCSI_BOOT_IPV6 = 24, 352 BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6 = 25, 353 BNX_DIR_TYPE_ISCSI_BOOT_CFG6 = 26, 354 BNX_DIR_TYPE_EXT_PHY = 27, 355 BNX_DIR_TYPE_SHARED_CFG = 40, 356 BNX_DIR_TYPE_PORT_CFG = 41, 357 BNX_DIR_TYPE_FUNC_CFG = 42, 358 BNX_DIR_TYPE_MGMT_CFG = 48, 359 BNX_DIR_TYPE_MGMT_DATA = 49, 360 BNX_DIR_TYPE_MGMT_WEB_DATA = 50, 361 BNX_DIR_TYPE_MGMT_WEB_META = 51, 362 BNX_DIR_TYPE_MGMT_EVENT_LOG = 52, 363 BNX_DIR_TYPE_MGMT_AUDIT_LOG = 53 364 }; 365 366 enum bnxnvm_pkglog_field_index { 367 BNX_PKG_LOG_FIELD_IDX_INSTALLED_TIMESTAMP = 0, 368 BNX_PKG_LOG_FIELD_IDX_PKG_DESCRIPTION = 1, 369 BNX_PKG_LOG_FIELD_IDX_PKG_VERSION = 2, 370 BNX_PKG_LOG_FIELD_IDX_PKG_TIMESTAMP = 3, 371 BNX_PKG_LOG_FIELD_IDX_PKG_CHECKSUM = 4, 372 BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS = 5, 373 BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK = 6 374 }; 375 376 #define BNX_DIR_ORDINAL_FIRST 0 377 #define BNX_DIR_EXT_NONE 0 378 379 struct bnxt_bar_info { 380 struct resource *res; 381 bus_space_tag_t tag; 382 bus_space_handle_t handle; 383 bus_size_t size; 384 int rid; 385 }; 386 387 struct bnxt_flow_ctrl { 388 bool rx; 389 bool tx; 390 bool autoneg; 391 }; 392 393 struct bnxt_link_info { 394 uint8_t media_type; 395 uint8_t transceiver; 396 uint8_t phy_addr; 397 uint8_t phy_link_status; 398 uint8_t wire_speed; 399 uint8_t loop_back; 400 uint8_t link_up; 401 uint8_t last_link_up; 402 uint8_t duplex; 403 uint8_t last_duplex; 404 uint8_t last_phy_type; 405 struct bnxt_flow_ctrl flow_ctrl; 406 struct bnxt_flow_ctrl last_flow_ctrl; 407 uint8_t duplex_setting; 408 uint8_t auto_mode; 409 #define PHY_VER_LEN 3 410 uint8_t phy_ver[PHY_VER_LEN]; 411 uint8_t phy_type; 412 #define BNXT_PHY_STATE_ENABLED 0 413 #define BNXT_PHY_STATE_DISABLED 1 414 uint8_t phy_state; 415 416 uint16_t link_speed; 417 uint16_t support_speeds; 418 uint16_t support_speeds2; 419 uint16_t support_pam4_speeds; 420 uint16_t auto_link_speeds; 421 uint16_t auto_link_speeds2; 422 uint16_t auto_pam4_link_speeds; 423 uint16_t force_link_speed; 424 uint16_t force_link_speeds2; 425 uint16_t force_pam4_link_speed; 426 427 bool force_pam4_speed; 428 bool force_speed2_nrz; 429 bool force_pam4_56_speed2; 430 bool force_pam4_112_speed2; 431 432 uint16_t advertising; 433 uint16_t advertising_pam4; 434 435 uint32_t preemphasis; 436 uint16_t support_auto_speeds; 437 uint16_t support_force_speeds; 438 uint16_t support_pam4_auto_speeds; 439 uint16_t support_pam4_force_speeds; 440 uint16_t support_auto_speeds2; 441 uint16_t support_force_speeds2; 442 #define BNXT_SIG_MODE_NRZ HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ 443 #define BNXT_SIG_MODE_PAM4 HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 444 #define BNXT_SIG_MODE_PAM4_112 HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4_112 445 uint8_t req_signal_mode; 446 447 uint8_t active_fec_sig_mode; 448 uint8_t sig_mode; 449 450 /* copy of requested setting */ 451 uint8_t autoneg; 452 #define BNXT_AUTONEG_SPEED 1 453 #define BNXT_AUTONEG_FLOW_CTRL 2 454 uint8_t req_duplex; 455 uint16_t req_link_speed; 456 uint8_t module_status; 457 struct hwrm_port_phy_qcfg_output phy_qcfg_resp; 458 uint8_t active_lanes; 459 }; 460 461 enum bnxt_phy_type { 462 BNXT_MEDIA_CR = 0, 463 BNXT_MEDIA_LR, 464 BNXT_MEDIA_SR, 465 BNXT_MEDIA_ER, 466 BNXT_MEDIA_KR, 467 BNXT_MEDIA_AC, 468 BNXT_MEDIA_BASECX, 469 BNXT_MEDIA_BASET, 470 BNXT_MEDIA_BASEKX, 471 BNXT_MEDIA_BASESGMII, 472 BNXT_MEDIA_END 473 }; 474 475 enum bnxt_cp_type { 476 BNXT_DEFAULT, 477 BNXT_TX, 478 BNXT_RX, 479 BNXT_SHARED 480 }; 481 482 struct bnxt_queue_info { 483 uint8_t queue_id; 484 uint8_t queue_profile; 485 }; 486 487 struct bnxt_func_info { 488 uint32_t fw_fid; 489 uint8_t mac_addr[ETHER_ADDR_LEN]; 490 uint16_t max_rsscos_ctxs; 491 uint16_t max_cp_rings; 492 uint16_t max_tx_rings; 493 uint16_t max_rx_rings; 494 uint16_t max_hw_ring_grps; 495 uint16_t max_irqs; 496 uint16_t max_l2_ctxs; 497 uint16_t max_vnics; 498 uint16_t max_stat_ctxs; 499 }; 500 501 struct bnxt_pf_info { 502 #define BNXT_FIRST_PF_FID 1 503 #define BNXT_FIRST_VF_FID 128 504 uint8_t port_id; 505 uint32_t first_vf_id; 506 uint16_t active_vfs; 507 uint16_t max_vfs; 508 uint32_t max_encap_records; 509 uint32_t max_decap_records; 510 uint32_t max_tx_em_flows; 511 uint32_t max_tx_wm_flows; 512 uint32_t max_rx_em_flows; 513 uint32_t max_rx_wm_flows; 514 unsigned long *vf_event_bmap; 515 uint16_t hwrm_cmd_req_pages; 516 void *hwrm_cmd_req_addr[4]; 517 bus_addr_t hwrm_cmd_req_dma_addr[4]; 518 }; 519 520 struct bnxt_vf_info { 521 uint16_t fw_fid; 522 uint8_t mac_addr[ETHER_ADDR_LEN]; 523 uint16_t max_rsscos_ctxs; 524 uint16_t max_cp_rings; 525 uint16_t max_tx_rings; 526 uint16_t max_rx_rings; 527 uint16_t max_hw_ring_grps; 528 uint16_t max_l2_ctxs; 529 uint16_t max_irqs; 530 uint16_t max_vnics; 531 uint16_t max_stat_ctxs; 532 uint32_t vlan; 533 #define BNXT_VF_QOS 0x1 534 #define BNXT_VF_SPOOFCHK 0x2 535 #define BNXT_VF_LINK_FORCED 0x4 536 #define BNXT_VF_LINK_UP 0x8 537 uint32_t flags; 538 uint32_t func_flags; /* func cfg flags */ 539 uint32_t min_tx_rate; 540 uint32_t max_tx_rate; 541 void *hwrm_cmd_req_addr; 542 bus_addr_t hwrm_cmd_req_dma_addr; 543 }; 544 545 #define BNXT_PF(softc) (!((softc)->flags & BNXT_FLAG_VF)) 546 #define BNXT_VF(softc) ((softc)->flags & BNXT_FLAG_VF) 547 548 struct bnxt_vlan_tag { 549 SLIST_ENTRY(bnxt_vlan_tag) next; 550 uint64_t filter_id; 551 uint16_t tag; 552 }; 553 554 struct bnxt_vnic_info { 555 uint16_t id; 556 uint16_t def_ring_grp; 557 uint16_t cos_rule; 558 uint16_t lb_rule; 559 uint16_t mru; 560 561 uint32_t rx_mask; 562 struct iflib_dma_info mc_list; 563 int mc_list_count; 564 #define BNXT_MAX_MC_ADDRS 16 565 566 uint32_t flags; 567 #define BNXT_VNIC_FLAG_DEFAULT 0x01 568 #define BNXT_VNIC_FLAG_BD_STALL 0x02 569 #define BNXT_VNIC_FLAG_VLAN_STRIP 0x04 570 571 uint64_t filter_id; 572 573 uint16_t rss_id; 574 uint32_t rss_hash_type; 575 uint8_t rss_hash_key[HW_HASH_KEY_SIZE]; 576 struct iflib_dma_info rss_hash_key_tbl; 577 struct iflib_dma_info rss_grp_tbl; 578 SLIST_HEAD(vlan_head, bnxt_vlan_tag) vlan_tags; 579 struct iflib_dma_info vlan_tag_list; 580 }; 581 582 struct bnxt_grp_info { 583 uint16_t stats_ctx; 584 uint16_t grp_id; 585 uint16_t rx_ring_id; 586 uint16_t cp_ring_id; 587 uint16_t ag_ring_id; 588 }; 589 590 #define EPOCH_ARR_SZ 4096 591 592 struct bnxt_ring { 593 uint64_t paddr; 594 vm_offset_t doorbell; 595 caddr_t vaddr; 596 struct bnxt_softc *softc; 597 uint32_t ring_size; /* Must be a power of two */ 598 uint16_t id; /* Logical ID */ 599 uint16_t phys_id; 600 uint16_t idx; 601 struct bnxt_full_tpa_start *tpa_start; 602 union { 603 u64 db_key64; 604 u32 db_key32; 605 }; 606 uint32_t db_ring_mask; 607 uint32_t db_epoch_mask; 608 uint8_t db_epoch_shift; 609 610 uint64_t epoch_arr[EPOCH_ARR_SZ]; 611 bool epoch_bit; 612 613 }; 614 615 struct bnxt_cp_ring { 616 struct bnxt_ring ring; 617 struct if_irq irq; 618 uint32_t cons; 619 uint32_t raw_cons; 620 bool v_bit; /* Value of valid bit */ 621 struct ctx_hw_stats *stats; 622 uint32_t stats_ctx_id; 623 uint32_t last_idx; /* Used by RX rings only 624 * set to the last read pidx 625 */ 626 uint64_t int_count; 627 uint8_t toggle; 628 uint8_t type; 629 #define Q_TYPE_TX 1 630 #define Q_TYPE_RX 2 631 }; 632 633 struct bnxt_full_tpa_start { 634 struct rx_tpa_start_cmpl low; 635 struct rx_tpa_start_cmpl_hi high; 636 }; 637 638 /* All the version information for the part */ 639 #define BNXT_VERSTR_SIZE (3*3+2+1) /* ie: "255.255.255\0" */ 640 #define BNXT_NAME_SIZE 17 641 #define FW_VER_STR_LEN 32 642 #define BC_HWRM_STR_LEN 21 643 struct bnxt_ver_info { 644 uint8_t hwrm_if_major; 645 uint8_t hwrm_if_minor; 646 uint8_t hwrm_if_update; 647 char hwrm_if_ver[BNXT_VERSTR_SIZE]; 648 char driver_hwrm_if_ver[BNXT_VERSTR_SIZE]; 649 char mgmt_fw_ver[FW_VER_STR_LEN]; 650 char netctrl_fw_ver[FW_VER_STR_LEN]; 651 char roce_fw_ver[FW_VER_STR_LEN]; 652 char fw_ver_str[FW_VER_STR_LEN]; 653 char phy_ver[BNXT_VERSTR_SIZE]; 654 char pkg_ver[64]; 655 656 char hwrm_fw_name[BNXT_NAME_SIZE]; 657 char mgmt_fw_name[BNXT_NAME_SIZE]; 658 char netctrl_fw_name[BNXT_NAME_SIZE]; 659 char roce_fw_name[BNXT_NAME_SIZE]; 660 char phy_vendor[BNXT_NAME_SIZE]; 661 char phy_partnumber[BNXT_NAME_SIZE]; 662 663 uint16_t chip_num; 664 uint8_t chip_rev; 665 uint8_t chip_metal; 666 uint8_t chip_bond_id; 667 uint8_t chip_type; 668 669 uint8_t hwrm_min_major; 670 uint8_t hwrm_min_minor; 671 uint8_t hwrm_min_update; 672 uint64_t fw_ver_code; 673 #define BNXT_FW_VER_CODE(maj, min, bld, rsv) \ 674 ((uint64_t)(maj) << 48 | (uint64_t)(min) << 32 | (uint64_t)(bld) << 16 | (rsv)) 675 #define BNXT_FW_MAJ(softc) ((softc)->ver_info->fw_ver_code >> 48) 676 #define BNXT_FW_MIN(softc) (((softc)->ver_info->fw_ver_code >> 32) & 0xffff) 677 #define BNXT_FW_BLD(softc) (((softc)->ver_info->fw_ver_code >> 16) & 0xffff) 678 #define BNXT_FW_RSV(softc) (((softc)->ver_info->fw_ver_code) & 0xffff) 679 680 struct sysctl_ctx_list ver_ctx; 681 struct sysctl_oid *ver_oid; 682 }; 683 684 struct bnxt_nvram_info { 685 uint16_t mfg_id; 686 uint16_t device_id; 687 uint32_t sector_size; 688 uint32_t size; 689 uint32_t reserved_size; 690 uint32_t available_size; 691 692 struct sysctl_ctx_list nvm_ctx; 693 struct sysctl_oid *nvm_oid; 694 }; 695 696 struct bnxt_func_qcfg { 697 uint16_t alloc_completion_rings; 698 uint16_t alloc_tx_rings; 699 uint16_t alloc_rx_rings; 700 uint16_t alloc_vnics; 701 }; 702 703 struct bnxt_hw_lro { 704 uint16_t enable; 705 uint16_t is_mode_gro; 706 uint16_t max_agg_segs; 707 uint16_t max_aggs; 708 uint32_t min_agg_len; 709 }; 710 711 /* The hardware supports certain page sizes. Use the supported page sizes 712 * to allocate the rings. 713 */ 714 #if (PAGE_SHIFT < 12) 715 #define BNXT_PAGE_SHIFT 12 716 #elif (PAGE_SHIFT <= 13) 717 #define BNXT_PAGE_SHIFT PAGE_SHIFT 718 #elif (PAGE_SHIFT < 16) 719 #define BNXT_PAGE_SHIFT 13 720 #else 721 #define BNXT_PAGE_SHIFT 16 722 #endif 723 724 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT) 725 726 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) 727 #define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES) 728 729 struct bnxt_ring_mem_info { 730 int nr_pages; 731 int page_size; 732 uint16_t flags; 733 #define BNXT_RMEM_VALID_PTE_FLAG 1 734 #define BNXT_RMEM_RING_PTE_FLAG 2 735 #define BNXT_RMEM_USE_FULL_PAGE_FLAG 4 736 uint16_t depth; 737 struct bnxt_ctx_mem_type *ctx_mem; 738 739 struct iflib_dma_info *pg_arr; 740 struct iflib_dma_info pg_tbl; 741 742 int vmem_size; 743 void **vmem; 744 }; 745 746 struct bnxt_ctx_pg_info { 747 uint32_t entries; 748 uint32_t nr_pages; 749 struct iflib_dma_info ctx_arr[MAX_CTX_PAGES]; 750 struct bnxt_ring_mem_info ring_mem; 751 struct bnxt_ctx_pg_info **ctx_pg_tbl; 752 }; 753 754 #define BNXT_MAX_TQM_SP_RINGS 1 755 #define BNXT_MAX_TQM_FP_LEGACY_RINGS 8 756 #define BNXT_MAX_TQM_FP_RINGS 9 757 #define BNXT_MAX_TQM_LEGACY_RINGS \ 758 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_LEGACY_RINGS) 759 #define BNXT_MAX_TQM_RINGS \ 760 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS) 761 762 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256 763 #define BNXT_BACKING_STORE_CFG_LEN \ 764 sizeof(struct hwrm_func_backing_store_cfg_input) 765 766 #define BNXT_SET_CTX_PAGE_ATTR(attr) \ 767 do { \ 768 if (BNXT_PAGE_SIZE == 0x2000) \ 769 attr = HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K; \ 770 else if (BNXT_PAGE_SIZE == 0x10000) \ 771 attr = HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K; \ 772 else \ 773 attr = HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K; \ 774 } while (0) 775 776 struct bnxt_ctx_mem_type { 777 u16 type; 778 u16 entry_size; 779 u32 flags; 780 #define BNXT_CTX_MEM_TYPE_VALID HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID 781 u32 instance_bmap; 782 u8 init_value; 783 u8 entry_multiple; 784 u16 init_offset; 785 #define BNXT_CTX_INIT_INVALID_OFFSET 0xffff 786 u32 max_entries; 787 u32 min_entries; 788 u8 last:1; 789 u8 mem_valid:1; 790 u8 split_entry_cnt; 791 #define BNXT_MAX_SPLIT_ENTRY 4 792 union { 793 struct { 794 u32 qp_l2_entries; 795 u32 qp_qp1_entries; 796 }; 797 u32 srq_l2_entries; 798 u32 cq_l2_entries; 799 u32 vnic_entries; 800 struct { 801 u32 mrav_av_entries; 802 u32 mrav_num_entries_units; 803 }; 804 u32 split[BNXT_MAX_SPLIT_ENTRY]; 805 }; 806 struct bnxt_ctx_pg_info *pg_info; 807 }; 808 809 #define BNXT_CTX_QP HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QP 810 #define BNXT_CTX_SRQ HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ 811 #define BNXT_CTX_CQ HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ 812 #define BNXT_CTX_VNIC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC 813 #define BNXT_CTX_STAT HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT 814 #define BNXT_CTX_STQM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING 815 #define BNXT_CTX_FTQM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING 816 #define BNXT_CTX_MRAV HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV 817 #define BNXT_CTX_TIM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM 818 #define BNXT_CTX_TKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TKC 819 #define BNXT_CTX_RKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RKC 820 #define BNXT_CTX_MTQM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING 821 #define BNXT_CTX_SQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SQ_DB_SHADOW 822 #define BNXT_CTX_RQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RQ_DB_SHADOW 823 #define BNXT_CTX_SRQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ_DB_SHADOW 824 #define BNXT_CTX_CQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW 825 #define BNXT_CTX_QTKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_TKC 826 #define BNXT_CTX_QRKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_RKC 827 #define BNXT_CTX_MAX (BNXT_CTX_TIM + 1) 828 #define BNXT_CTX_L2_MAX (BNXT_CTX_FTQM + 1) 829 830 #define BNXT_CTX_V2_MAX (HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_ROCE_HWRM_TRACE + 1) 831 #define BNXT_CTX_SRT_TRACE HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRT_TRACE 832 #define BNXT_CTX_ROCE_HWRM_TRACE HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_ROCE_HWRM_TRACE 833 #define BNXT_CTX_INV ((u16)-1) 834 835 struct bnxt_ctx_mem_info { 836 u8 tqm_fp_rings_count; 837 838 u32 flags; 839 #define BNXT_CTX_FLAG_INITED 0x01 840 struct bnxt_ctx_mem_type ctx_arr[BNXT_CTX_V2_MAX]; 841 }; 842 843 struct bnxt_hw_resc { 844 uint16_t min_rsscos_ctxs; 845 uint16_t max_rsscos_ctxs; 846 uint16_t min_cp_rings; 847 uint16_t max_cp_rings; 848 uint16_t resv_cp_rings; 849 uint16_t min_tx_rings; 850 uint16_t max_tx_rings; 851 uint16_t resv_tx_rings; 852 uint16_t max_tx_sch_inputs; 853 uint16_t min_rx_rings; 854 uint16_t max_rx_rings; 855 uint16_t resv_rx_rings; 856 uint16_t min_hw_ring_grps; 857 uint16_t max_hw_ring_grps; 858 uint16_t resv_hw_ring_grps; 859 uint16_t min_l2_ctxs; 860 uint16_t max_l2_ctxs; 861 uint16_t min_vnics; 862 uint16_t max_vnics; 863 uint16_t resv_vnics; 864 uint16_t min_stat_ctxs; 865 uint16_t max_stat_ctxs; 866 uint16_t resv_stat_ctxs; 867 uint16_t max_nqs; 868 uint16_t max_irqs; 869 uint16_t resv_irqs; 870 }; 871 872 enum bnxt_type_ets { 873 BNXT_TYPE_ETS_TSA = 0, 874 BNXT_TYPE_ETS_PRI2TC, 875 BNXT_TYPE_ETS_TCBW, 876 BNXT_TYPE_ETS_MAX 877 }; 878 879 static const char *const BNXT_ETS_TYPE_STR[] = { 880 "tsa", 881 "pri2tc", 882 "tcbw", 883 }; 884 885 static const char *const BNXT_ETS_HELP_STR[] = { 886 "X is 1 (strict), 0 (ets)", 887 "TC values for pri 0 to 7", 888 "TC BW values for pri 0 to 7, Sum should be 100", 889 }; 890 891 #define BNXT_HWRM_MAX_REQ_LEN (softc->hwrm_max_req_len) 892 893 struct bnxt_softc_list { 894 SLIST_ENTRY(bnxt_softc_list) next; 895 struct bnxt_softc *softc; 896 }; 897 898 #ifndef BIT_ULL 899 #define BIT_ULL(nr) (1ULL << (nr)) 900 #endif 901 902 struct bnxt_aux_dev { 903 struct auxiliary_device aux_dev; 904 struct bnxt_en_dev *edev; 905 int id; 906 }; 907 908 struct bnxt_msix_tbl { 909 uint32_t entry; 910 uint32_t vector; 911 }; 912 913 enum bnxt_health_severity { 914 SEVERITY_NORMAL = 0, 915 SEVERITY_WARNING, 916 SEVERITY_RECOVERABLE, 917 SEVERITY_FATAL, 918 }; 919 920 enum bnxt_health_remedy { 921 REMEDY_DEVLINK_RECOVER, 922 REMEDY_POWER_CYCLE_DEVICE, 923 REMEDY_POWER_CYCLE_HOST, 924 REMEDY_FW_UPDATE, 925 REMEDY_HW_REPLACE, 926 }; 927 928 struct bnxt_fw_health { 929 u32 flags; 930 u32 polling_dsecs; 931 u32 master_func_wait_dsecs; 932 u32 normal_func_wait_dsecs; 933 u32 post_reset_wait_dsecs; 934 u32 post_reset_max_wait_dsecs; 935 u32 regs[4]; 936 u32 mapped_regs[4]; 937 #define BNXT_FW_HEALTH_REG 0 938 #define BNXT_FW_HEARTBEAT_REG 1 939 #define BNXT_FW_RESET_CNT_REG 2 940 #define BNXT_FW_RESET_INPROG_REG 3 941 u32 fw_reset_inprog_reg_mask; 942 u32 last_fw_heartbeat; 943 u32 last_fw_reset_cnt; 944 u8 enabled:1; 945 u8 primary:1; 946 u8 status_reliable:1; 947 u8 resets_reliable:1; 948 u8 tmr_multiplier; 949 u8 tmr_counter; 950 u8 fw_reset_seq_cnt; 951 u32 fw_reset_seq_regs[16]; 952 u32 fw_reset_seq_vals[16]; 953 u32 fw_reset_seq_delay_msec[16]; 954 u32 echo_req_data1; 955 u32 echo_req_data2; 956 struct devlink_health_reporter *fw_reporter; 957 struct mutex lock; 958 enum bnxt_health_severity severity; 959 enum bnxt_health_remedy remedy; 960 u32 arrests; 961 u32 discoveries; 962 u32 survivals; 963 u32 fatalities; 964 u32 diagnoses; 965 }; 966 967 #define BNXT_FW_HEALTH_REG_TYPE_MASK 3 968 #define BNXT_FW_HEALTH_REG_TYPE_CFG 0 969 #define BNXT_FW_HEALTH_REG_TYPE_GRC 1 970 #define BNXT_FW_HEALTH_REG_TYPE_BAR0 2 971 #define BNXT_FW_HEALTH_REG_TYPE_BAR1 3 972 973 #define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK) 974 #define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK) 975 976 #define BNXT_FW_HEALTH_WIN_BASE 0x3000 977 #define BNXT_FW_HEALTH_WIN_MAP_OFF 8 978 979 #define BNXT_FW_HEALTH_WIN_OFF(reg) (BNXT_FW_HEALTH_WIN_BASE + \ 980 ((reg) & BNXT_GRC_OFFSET_MASK)) 981 982 #define BNXT_FW_STATUS_HEALTH_MSK 0xffff 983 #define BNXT_FW_STATUS_HEALTHY 0x8000 984 #define BNXT_FW_STATUS_SHUTDOWN 0x100000 985 #define BNXT_FW_STATUS_RECOVERING 0x400000 986 987 #define BNXT_FW_IS_HEALTHY(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\ 988 BNXT_FW_STATUS_HEALTHY) 989 990 #define BNXT_FW_IS_BOOTING(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \ 991 BNXT_FW_STATUS_HEALTHY) 992 993 #define BNXT_FW_IS_ERR(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \ 994 BNXT_FW_STATUS_HEALTHY) 995 996 #define BNXT_FW_IS_RECOVERING(sts) (BNXT_FW_IS_ERR(sts) && \ 997 ((sts) & BNXT_FW_STATUS_RECOVERING)) 998 999 #define BNXT_FW_RETRY 5 1000 #define BNXT_FW_IF_RETRY 10 1001 #define BNXT_FW_SLOT_RESET_RETRY 4 1002 1003 #define BNXT_GRCPF_REG_CHIMP_COMM 0x0 1004 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 1005 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 1006 #define BNXT_GRCPF_REG_SYNC_TIME 0x480 1007 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ 0x488 1008 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_PER_MSK 0xffffffUL 1009 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_PER_SFT 0 1010 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_VAL_MSK 0x1f000000UL 1011 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_VAL_SFT 24 1012 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_SIGN_MSK 0x20000000UL 1013 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_SIGN_SFT 29 1014 1015 #define BNXT_GRC_REG_STATUS_P5 0x520 1016 1017 #define BNXT_GRCPF_REG_KONG_COMM 0xA00 1018 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00 1019 1020 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014 1021 #define BNXT_CAG_REG_BASE 0x300000 1022 1023 #define BNXT_GRC_REG_CHIP_NUM 0x48 1024 #define BNXT_GRC_REG_BASE 0x260000 1025 1026 #define BNXT_TS_REG_TIMESYNC_TS0_LOWER 0x640180c 1027 #define BNXT_TS_REG_TIMESYNC_TS0_UPPER 0x6401810 1028 1029 #define BNXT_GRC_BASE_MASK 0xfffff000 1030 #define BNXT_GRC_OFFSET_MASK 0x00000ffc 1031 1032 #define NQE_CN_TYPE(type) ((type) & NQ_CN_TYPE_MASK) 1033 #define NQE_CN_TOGGLE(type) (((type) & NQ_CN_TOGGLE_MASK) >> \ 1034 NQ_CN_TOGGLE_SFT) 1035 1036 #define DB_EPOCH(ring, idx) (((idx) & (ring)->db_epoch_mask) << \ 1037 ((ring)->db_epoch_shift)) 1038 1039 #define DB_TOGGLE(tgl) ((tgl) << DBR_TOGGLE_SFT) 1040 1041 #define DB_RING_IDX_CMP(ring, idx) (((idx) & (ring)->db_ring_mask) | \ 1042 DB_EPOCH(ring, idx)) 1043 1044 #define DB_RING_IDX(ring, idx, bit) (((idx) & (ring)->db_ring_mask) | \ 1045 ((bit) << (24))) 1046 1047 struct bnxt_softc { 1048 device_t dev; 1049 if_ctx_t ctx; 1050 if_softc_ctx_t scctx; 1051 if_shared_ctx_t sctx; 1052 if_t ifp; 1053 uint32_t domain; 1054 uint32_t bus; 1055 uint32_t slot; 1056 uint32_t function; 1057 uint32_t dev_fn; 1058 struct ifmedia *media; 1059 struct bnxt_ctx_mem_info *ctx_mem; 1060 struct bnxt_hw_resc hw_resc; 1061 struct bnxt_softc_list list; 1062 1063 struct bnxt_bar_info hwrm_bar; 1064 struct bnxt_bar_info doorbell_bar; 1065 struct bnxt_link_info link_info; 1066 #define BNXT_FLAG_VF 0x0001 1067 #define BNXT_FLAG_NPAR 0x0002 1068 #define BNXT_FLAG_WOL_CAP 0x0004 1069 #define BNXT_FLAG_SHORT_CMD 0x0008 1070 #define BNXT_FLAG_FW_CAP_NEW_RM 0x0010 1071 #define BNXT_FLAG_CHIP_P5 0x0020 1072 #define BNXT_FLAG_TPA 0x0040 1073 #define BNXT_FLAG_FW_CAP_EXT_STATS 0x0080 1074 #define BNXT_FLAG_MULTI_HOST 0x0100 1075 #define BNXT_FLAG_MULTI_ROOT 0x0200 1076 #define BNXT_FLAG_ROCEV1_CAP 0x0400 1077 #define BNXT_FLAG_ROCEV2_CAP 0x0800 1078 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | BNXT_FLAG_ROCEV2_CAP) 1079 #define BNXT_FLAG_CHIP_P7 0x1000 1080 uint32_t flags; 1081 #define BNXT_STATE_LINK_CHANGE (0) 1082 #define BNXT_STATE_MAX (BNXT_STATE_LINK_CHANGE + 1) 1083 bitstr_t *state_bv; 1084 1085 uint32_t total_irqs; 1086 struct bnxt_msix_tbl *irq_tbl; 1087 1088 struct bnxt_func_info func; 1089 struct bnxt_func_qcfg fn_qcfg; 1090 struct bnxt_pf_info pf; 1091 struct bnxt_vf_info vf; 1092 1093 uint16_t hwrm_cmd_seq; 1094 uint32_t hwrm_cmd_timeo; /* milliseconds */ 1095 struct iflib_dma_info hwrm_cmd_resp; 1096 struct iflib_dma_info hwrm_short_cmd_req_addr; 1097 /* Interrupt info for HWRM */ 1098 struct if_irq irq; 1099 struct mtx hwrm_lock; 1100 uint16_t hwrm_max_req_len; 1101 uint16_t hwrm_max_ext_req_len; 1102 uint32_t hwrm_spec_code; 1103 1104 #define BNXT_MAX_QUEUE 8 1105 uint8_t max_tc; 1106 uint8_t max_lltc; 1107 struct bnxt_queue_info tx_q_info[BNXT_MAX_QUEUE]; 1108 struct bnxt_queue_info rx_q_info[BNXT_MAX_QUEUE]; 1109 uint8_t tc_to_qidx[BNXT_MAX_QUEUE]; 1110 uint8_t tx_q_ids[BNXT_MAX_QUEUE]; 1111 uint8_t rx_q_ids[BNXT_MAX_QUEUE]; 1112 uint8_t tx_max_q; 1113 uint8_t rx_max_q; 1114 uint8_t is_asym_q; 1115 1116 struct bnxt_ieee_ets *ieee_ets; 1117 struct bnxt_ieee_pfc *ieee_pfc; 1118 uint8_t dcbx_cap; 1119 uint8_t default_pri; 1120 uint8_t max_dscp_value; 1121 1122 uint64_t admin_ticks; 1123 struct iflib_dma_info hw_rx_port_stats; 1124 struct iflib_dma_info hw_tx_port_stats; 1125 struct rx_port_stats *rx_port_stats; 1126 struct tx_port_stats *tx_port_stats; 1127 1128 struct iflib_dma_info hw_tx_port_stats_ext; 1129 struct iflib_dma_info hw_rx_port_stats_ext; 1130 struct tx_port_stats_ext *tx_port_stats_ext; 1131 struct rx_port_stats_ext *rx_port_stats_ext; 1132 1133 uint16_t fw_rx_stats_ext_size; 1134 uint16_t fw_tx_stats_ext_size; 1135 uint16_t hw_ring_stats_size; 1136 1137 uint8_t tx_pri2cos_idx[8]; 1138 uint8_t rx_pri2cos_idx[8]; 1139 bool pri2cos_valid; 1140 1141 uint64_t tx_bytes_pri[8]; 1142 uint64_t tx_packets_pri[8]; 1143 uint64_t rx_bytes_pri[8]; 1144 uint64_t rx_packets_pri[8]; 1145 1146 uint8_t port_count; 1147 int num_cp_rings; 1148 1149 struct bnxt_cp_ring *nq_rings; 1150 1151 struct bnxt_ring *tx_rings; 1152 struct bnxt_cp_ring *tx_cp_rings; 1153 struct iflib_dma_info tx_stats[BNXT_MAX_NUM_QUEUES]; 1154 int ntxqsets; 1155 1156 struct bnxt_vnic_info vnic_info; 1157 struct bnxt_ring *ag_rings; 1158 struct bnxt_ring *rx_rings; 1159 struct bnxt_cp_ring *rx_cp_rings; 1160 struct bnxt_grp_info *grp_info; 1161 struct iflib_dma_info rx_stats[BNXT_MAX_NUM_QUEUES]; 1162 int nrxqsets; 1163 uint16_t rx_buf_size; 1164 1165 struct bnxt_cp_ring def_cp_ring; 1166 struct bnxt_cp_ring def_nq_ring; 1167 struct iflib_dma_info def_cp_ring_mem; 1168 struct iflib_dma_info def_nq_ring_mem; 1169 struct task def_cp_task; 1170 int db_size; 1171 int db_offset; 1172 int legacy_db_size; 1173 struct bnxt_doorbell_ops db_ops; 1174 1175 struct sysctl_ctx_list hw_stats; 1176 struct sysctl_oid *hw_stats_oid; 1177 struct sysctl_ctx_list hw_lro_ctx; 1178 struct sysctl_oid *hw_lro_oid; 1179 struct sysctl_ctx_list flow_ctrl_ctx; 1180 struct sysctl_oid *flow_ctrl_oid; 1181 struct sysctl_ctx_list dcb_ctx; 1182 struct sysctl_oid *dcb_oid; 1183 1184 struct bnxt_ver_info *ver_info; 1185 struct bnxt_nvram_info *nvm_info; 1186 bool wol; 1187 bool is_dev_init; 1188 struct bnxt_hw_lro hw_lro; 1189 uint8_t wol_filter_id; 1190 uint16_t rx_coal_usecs; 1191 uint16_t rx_coal_usecs_irq; 1192 uint16_t rx_coal_frames; 1193 uint16_t rx_coal_frames_irq; 1194 uint16_t tx_coal_usecs; 1195 uint16_t tx_coal_usecs_irq; 1196 uint16_t tx_coal_frames; 1197 uint16_t tx_coal_frames_irq; 1198 1199 #define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2) 1200 #define BNXT_DEF_STATS_COAL_TICKS 1000000 1201 #define BNXT_MIN_STATS_COAL_TICKS 250000 1202 #define BNXT_MAX_STATS_COAL_TICKS 1000000 1203 1204 uint64_t fw_cap; 1205 #define BNXT_FW_CAP_SHORT_CMD BIT_ULL(0) 1206 #define BNXT_FW_CAP_LLDP_AGENT BIT_ULL(1) 1207 #define BNXT_FW_CAP_DCBX_AGENT BIT_ULL(2) 1208 #define BNXT_FW_CAP_NEW_RM BIT_ULL(3) 1209 #define BNXT_FW_CAP_IF_CHANGE BIT_ULL(4) 1210 #define BNXT_FW_CAP_LINK_ADMIN BIT_ULL(5) 1211 #define BNXT_FW_CAP_VF_RES_MIN_GUARANTEED BIT_ULL(6) 1212 #define BNXT_FW_CAP_KONG_MB_CHNL BIT_ULL(7) 1213 #define BNXT_FW_CAP_ADMIN_MTU BIT_ULL(8) 1214 #define BNXT_FW_CAP_ADMIN_PF BIT_ULL(9) 1215 #define BNXT_FW_CAP_OVS_64BIT_HANDLE BIT_ULL(10) 1216 #define BNXT_FW_CAP_TRUSTED_VF BIT_ULL(11) 1217 #define BNXT_FW_CAP_VF_VNIC_NOTIFY BIT_ULL(12) 1218 #define BNXT_FW_CAP_ERROR_RECOVERY BIT_ULL(13) 1219 #define BNXT_FW_CAP_PKG_VER BIT_ULL(14) 1220 #define BNXT_FW_CAP_CFA_ADV_FLOW BIT_ULL(15) 1221 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 BIT_ULL(16) 1222 #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED BIT_ULL(17) 1223 #define BNXT_FW_CAP_EXT_STATS_SUPPORTED BIT_ULL(18) 1224 #define BNXT_FW_CAP_SECURE_MODE BIT_ULL(19) 1225 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT_ULL(20) 1226 #define BNXT_FW_CAP_HOT_RESET BIT_ULL(21) 1227 #define BNXT_FW_CAP_CRASHDUMP BIT_ULL(23) 1228 #define BNXT_FW_CAP_VLAN_RX_STRIP BIT_ULL(24) 1229 #define BNXT_FW_CAP_VLAN_TX_INSERT BIT_ULL(25) 1230 #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED BIT_ULL(26) 1231 #define BNXT_FW_CAP_CFA_EEM BIT_ULL(27) 1232 #define BNXT_FW_CAP_DBG_QCAPS BIT_ULL(29) 1233 #define BNXT_FW_CAP_RING_MONITOR BIT_ULL(30) 1234 #define BNXT_FW_CAP_ECN_STATS BIT_ULL(31) 1235 #define BNXT_FW_CAP_TRUFLOW BIT_ULL(32) 1236 #define BNXT_FW_CAP_VF_CFG_FOR_PF BIT_ULL(33) 1237 #define BNXT_FW_CAP_PTP_PPS BIT_ULL(34) 1238 #define BNXT_FW_CAP_HOT_RESET_IF BIT_ULL(35) 1239 #define BNXT_FW_CAP_LIVEPATCH BIT_ULL(36) 1240 #define BNXT_FW_CAP_NPAR_1_2 BIT_ULL(37) 1241 #define BNXT_FW_CAP_RSS_HASH_TYPE_DELTA BIT_ULL(38) 1242 #define BNXT_FW_CAP_PTP_RTC BIT_ULL(39) 1243 #define BNXT_FW_CAP_TRUFLOW_EN BIT_ULL(40) 1244 #define BNXT_TRUFLOW_EN(bp) ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN) 1245 #define BNXT_FW_CAP_RX_ALL_PKT_TS BIT_ULL(41) 1246 #define BNXT_FW_CAP_BACKING_STORE_V2 BIT_ULL(42) 1247 #define BNXT_FW_CAP_DBR_SUPPORTED BIT_ULL(43) 1248 #define BNXT_FW_CAP_GENERIC_STATS BIT_ULL(44) 1249 #define BNXT_FW_CAP_DBR_PACING_SUPPORTED BIT_ULL(45) 1250 #define BNXT_FW_CAP_PTP_PTM BIT_ULL(46) 1251 #define BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO BIT_ULL(47) 1252 #define BNXT_FW_CAP_ENABLE_RDMA_SRIOV BIT_ULL(48) 1253 #define BNXT_FW_CAP_RSS_TCAM BIT_ULL(49) 1254 1255 #define BNXT_FW_CAP_SW_MAX_RESOURCE_LIMITS BIT_ULL(61) 1256 #define BNXT_SW_RES_LMT(bp) ((bp)->fw_cap & BNXT_FW_CAP_SW_MAX_RESOURCE_LIMITS) 1257 1258 uint32_t lpi_tmr_lo; 1259 uint32_t lpi_tmr_hi; 1260 /* copied from flags and flags2 in hwrm_port_phy_qcaps_output */ 1261 uint16_t phy_flags; 1262 #define BNXT_PHY_FL_EEE_CAP HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED 1263 #define BNXT_PHY_FL_EXT_LPBK HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED 1264 #define BNXT_PHY_FL_AN_PHY_LPBK HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED 1265 #define BNXT_PHY_FL_SHARED_PORT_CFG HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED 1266 #define BNXT_PHY_FL_PORT_STATS_NO_RESET HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 1267 #define BNXT_PHY_FL_NO_PHY_LPBK HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 1268 #define BNXT_PHY_FL_FW_MANAGED_LKDN HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_FW_MANAGED_LINK_DOWN 1269 #define BNXT_PHY_FL_NO_FCS HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_NO_FCS 1270 #define BNXT_PHY_FL_NO_PAUSE (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PAUSE_UNSUPPORTED << 8) 1271 #define BNXT_PHY_FL_NO_PFC (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED << 8) 1272 #define BNXT_PHY_FL_BANK_SEL (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_BANK_ADDR_SUPPORTED << 8) 1273 #define BNXT_PHY_FL_SPEEDS2 (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_SPEEDS2_SUPPORTED << 8) 1274 struct bnxt_aux_dev *aux_dev; 1275 struct net_device *net_dev; 1276 struct mtx en_ops_lock; 1277 uint8_t port_partition_type; 1278 struct bnxt_en_dev *edev; 1279 unsigned long state; 1280 #define BNXT_STATE_OPEN 0 1281 #define BNXT_STATE_IN_SP_TASK 1 1282 #define BNXT_STATE_READ_STATS 2 1283 #define BNXT_STATE_FW_RESET_DET 3 1284 #define BNXT_STATE_IN_FW_RESET 4 1285 #define BNXT_STATE_ABORT_ERR 5 1286 #define BNXT_STATE_FW_FATAL_COND 6 1287 #define BNXT_STATE_DRV_REGISTERED 7 1288 #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN 8 1289 #define BNXT_STATE_NAPI_DISABLED 9 1290 #define BNXT_STATE_L2_FILTER_RETRY 10 1291 #define BNXT_STATE_FW_ACTIVATE 11 1292 #define BNXT_STATE_RECOVER 12 1293 #define BNXT_STATE_FW_NON_FATAL_COND 13 1294 #define BNXT_STATE_FW_ACTIVATE_RESET 14 1295 #define BNXT_STATE_HALF_OPEN 15 1296 #define BNXT_NO_FW_ACCESS(bp) \ 1297 test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) 1298 struct pci_dev *pdev; 1299 1300 struct work_struct sp_task; 1301 unsigned long sp_event; 1302 #define BNXT_RX_MASK_SP_EVENT 0 1303 #define BNXT_RX_NTP_FLTR_SP_EVENT 1 1304 #define BNXT_LINK_CHNG_SP_EVENT 2 1305 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3 1306 #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4 1307 #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5 1308 #define BNXT_RESET_TASK_SP_EVENT 6 1309 #define BNXT_RST_RING_SP_EVENT 7 1310 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8 1311 #define BNXT_PERIODIC_STATS_SP_EVENT 9 1312 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10 1313 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11 1314 #define BNXT_GENEVE_ADD_PORT_SP_EVENT 12 1315 #define BNXT_GENEVE_DEL_PORT_SP_EVENT 13 1316 #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14 1317 #define BNXT_FLOW_STATS_SP_EVENT 15 1318 #define BNXT_UPDATE_PHY_SP_EVENT 16 1319 #define BNXT_RING_COAL_NOW_SP_EVENT 17 1320 #define BNXT_FW_RESET_NOTIFY_SP_EVENT 18 1321 #define BNXT_FW_EXCEPTION_SP_EVENT 19 1322 #define BNXT_VF_VNIC_CHANGE_SP_EVENT 20 1323 #define BNXT_LINK_CFG_CHANGE_SP_EVENT 21 1324 #define BNXT_PTP_CURRENT_TIME_EVENT 22 1325 #define BNXT_FW_ECHO_REQUEST_SP_EVENT 23 1326 #define BNXT_VF_CFG_CHNG_SP_EVENT 24 1327 1328 struct delayed_work fw_reset_task; 1329 int fw_reset_state; 1330 #define BNXT_FW_RESET_STATE_POLL_VF 1 1331 #define BNXT_FW_RESET_STATE_RESET_FW 2 1332 #define BNXT_FW_RESET_STATE_ENABLE_DEV 3 1333 #define BNXT_FW_RESET_STATE_POLL_FW 4 1334 #define BNXT_FW_RESET_STATE_OPENING 5 1335 #define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6 1336 u16 fw_reset_min_dsecs; 1337 #define BNXT_DFLT_FW_RST_MIN_DSECS 20 1338 u16 fw_reset_max_dsecs; 1339 #define BNXT_DFLT_FW_RST_MAX_DSECS 60 1340 unsigned long fw_reset_timestamp; 1341 1342 struct bnxt_fw_health *fw_health; 1343 char board_partno[64]; 1344 }; 1345 1346 struct bnxt_filter_info { 1347 STAILQ_ENTRY(bnxt_filter_info) next; 1348 uint64_t fw_l2_filter_id; 1349 #define INVALID_MAC_INDEX ((uint16_t)-1) 1350 uint16_t mac_index; 1351 1352 /* Filter Characteristics */ 1353 uint32_t flags; 1354 uint32_t enables; 1355 uint8_t l2_addr[ETHER_ADDR_LEN]; 1356 uint8_t l2_addr_mask[ETHER_ADDR_LEN]; 1357 uint16_t l2_ovlan; 1358 uint16_t l2_ovlan_mask; 1359 uint16_t l2_ivlan; 1360 uint16_t l2_ivlan_mask; 1361 uint8_t t_l2_addr[ETHER_ADDR_LEN]; 1362 uint8_t t_l2_addr_mask[ETHER_ADDR_LEN]; 1363 uint16_t t_l2_ovlan; 1364 uint16_t t_l2_ovlan_mask; 1365 uint16_t t_l2_ivlan; 1366 uint16_t t_l2_ivlan_mask; 1367 uint8_t tunnel_type; 1368 uint16_t mirror_vnic_id; 1369 uint32_t vni; 1370 uint8_t pri_hint; 1371 uint64_t l2_filter_id_hint; 1372 }; 1373 1374 #define I2C_DEV_ADDR_A0 0xa0 1375 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64 1376 1377 /* Function declarations */ 1378 void bnxt_report_link(struct bnxt_softc *softc); 1379 bool bnxt_check_hwrm_version(struct bnxt_softc *softc); 1380 struct bnxt_softc *bnxt_find_dev(uint32_t domain, uint32_t bus, uint32_t dev_fn, char *name); 1381 int bnxt_read_sfp_module_eeprom_info(struct bnxt_softc *bp, uint16_t i2c_addr, 1382 uint16_t page_number, uint8_t bank, bool bank_sel_en, uint16_t start_addr, 1383 uint16_t data_length, uint8_t *buf); 1384 void bnxt_dcb_init(struct bnxt_softc *softc); 1385 void bnxt_dcb_free(struct bnxt_softc *softc); 1386 uint8_t bnxt_dcb_setdcbx(struct bnxt_softc *softc, uint8_t mode); 1387 uint8_t bnxt_dcb_getdcbx(struct bnxt_softc *softc); 1388 int bnxt_dcb_ieee_getets(struct bnxt_softc *softc, struct bnxt_ieee_ets *ets); 1389 int bnxt_dcb_ieee_setets(struct bnxt_softc *softc, struct bnxt_ieee_ets *ets); 1390 uint8_t get_phy_type(struct bnxt_softc *softc); 1391 int bnxt_dcb_ieee_getpfc(struct bnxt_softc *softc, struct bnxt_ieee_pfc *pfc); 1392 int bnxt_dcb_ieee_setpfc(struct bnxt_softc *softc, struct bnxt_ieee_pfc *pfc); 1393 int bnxt_dcb_ieee_setapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app); 1394 int bnxt_dcb_ieee_delapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app); 1395 int bnxt_dcb_ieee_listapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app, 1396 size_t nitems, int *num_inputs); 1397 1398 #endif /* _BNXT_H */ 1399