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Searched refs:fdiv (Results 1 – 25 of 45) sorted by relevance

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/freebsd/sys/powerpc/powerpc/
H A Dclock.c260 uint32_t fdiv; in decr_et_start() local
273 fdiv = (decr_et.et_frequency * first) >> 32; in decr_et_start()
275 fdiv = s->div; in decr_et_start()
285 mtdec(fdiv); in decr_et_start()
288 mtdec(fdiv); in decr_et_start()
/freebsd/lib/libc/arm/aeabi/
H A Daeabi_vfp_float.S166 AEABI_ENTRY(fdiv)
171 AEABI_END(fdiv)
H A Daeabi_float.c72 float32 AEABI_FUNC2(fdiv, float32, float32_div) in AEABI_FUNC2()
/freebsd/sys/dev/acpica/
H A Dacpi_hpet.c210 uint32_t fdiv, now; in hpet_start() local
221 fdiv = (sc->freq * first) >> 32; in hpet_start()
223 fdiv = t->div; in hpet_start()
229 t->next = now + fdiv; in hpet_start()
247 fdiv *= 2; in hpet_start()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat64InstrInfo.td140 def : PatFprFpr<fdiv, FDIV_D, FPR64>;
149 def : Pat<(fdiv fpimm1, (fsqrt FPR64:$fj)), (FRSQRT_D FPR64:$fj)>;
252 def : Pat<(fdiv fpimm1, FPR64:$src), (FRECIP_D $src)>;
H A DLoongArchFloat32InstrInfo.td172 def : PatFprFpr<fdiv, FDIV_S, FPR32>;
181 def : Pat<(fdiv fpimm1, (fsqrt FPR32:$fj)), (FRSQRT_S FPR32:$fj)>;
289 def : Pat<(fdiv fpimm1, FPR32:$src), (FRECIP_S $src)>;
H A DLoongArchLASXInstrInfo.td1500 defm : PatXrXrF<fdiv, "XVFDIV">;
1538 def : Pat<(fdiv vsplatf32_fpimm_eq_1, v8f32:$xj),
1540 def : Pat<(fdiv vsplatf64_fpimm_eq_1, v4f64:$xj),
1544 def : Pat<(fdiv vsplatf32_fpimm_eq_1, (fsqrt v8f32:$xj)),
1546 def : Pat<(fdiv vsplatf64_fpimm_eq_1, (fsqrt v4f64:$xj)),
H A DLoongArchLSXInstrInfo.td1700 defm : PatVrVrF<fdiv, "VFDIV">;
1738 def : Pat<(fdiv vsplatf32_fpimm_eq_1, v4f32:$vj),
1740 def : Pat<(fdiv vsplatf64_fpimm_eq_1, v2f64:$vj),
1744 def : Pat<(fdiv vsplatf32_fpimm_eq_1, (fsqrt v4f32:$vj)),
1746 def : Pat<(fdiv vsplatf64_fpimm_eq_1, (fsqrt v2f64:$vj)),
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrAsmAlias.td560 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
561 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
572 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
591 defm : FpUnaryAlias<"fdiv", DIV_FST0r, 0>;
592 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0, 0>;
594 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0, 0>;
602 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
608 def : InstAlias<"fdiv{|r}p\t{$op, %st|st, $op}", (DIVR_FPrST0 RSTi:$op), 0>;
609 def : InstAlias<"fdiv{r|}p\t{$op, %st|st, $op}", (DIV_FPrST0 RSTi:$op), 0>;
H A DX86InstrFPStack.td219 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
243 def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st, $op|$op, st}">;
244 def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t{%st, $op|$op, st}">;
245 def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t{$op, %st|st, $op}">;
246 def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st, $op|$op, st}">;
247 def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t{%st, $op|$op, st}">;
/freebsd/sys/powerpc/fpu/
H A Dfpu_emu.c126 FPU_EMU_EVCNT_DECL(fdiv);
607 FPU_EMU_EVCNT_INCR(fdiv); in fpu_execute()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoQ.td53 defm FDIV_Q : FPALU_rr_frm_m<0b0001111, "fdiv.q", Ext>;
H A DRISCVSchedGenericOOO.td21 // * Floating-point fdiv/fsqrt instructions: 9-21 cycles.
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td1079 [(set f64:$dst, (fdiv f64imm_1, f64:$b))]>;
1084 [(set f64:$dst, (fdiv f64:$a, f64:$b))]>;
1089 [(set f64:$dst, (fdiv f64:$a, fpimm:$b))]>;
1091 // fdiv will be converted to rcp
1092 // fneg (fdiv 1.0, X) => fneg (rcp.rn X)
1093 def : Pat<(fdiv f64imm_neg1, f64:$b),
1101 (fdiv node:$a, node:$b), [{
1135 (fdiv node:$a, node:$b), [{
1163 (fdiv node:$a, node:$b), [{
1189 def : Pat<(fdiv f32imm_1, f32:$b), (FRCP32r_prec $b, NoFTZ)>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td27 def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
36 defm FDIV : ADDS_MMM<"div.d", II_DIV_D, 0, fdiv>,
H A DMipsInstrFPU.td670 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
672 defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>,
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFloat.td52 defm DIV : BinaryFP<fdiv, "div ", 0x95, 0xa3>;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td125 defm FDIV : FT_XYZ<0b011000, "fdiv", BinOpFrag<(fdiv node:$LHS, node:$RHS)>>;
H A DCSKYInstrInfoF2.td45 defm f2FDIV : F2_XYZ_T<0b011000, "fdiv", BinOpFrag<(fdiv node:$LHS, node:$RHS)>>;
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def329 // llvm.vp.fdiv(x,y,mask,vlen)
330 HELPER_REGISTER_BINARY_FP_VP(fdiv, VP_FDIV, FDiv, FDIV)
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/
H A DSelectionDAGCompat.td111 def : GINodeEquiv<G_FDIV, fdiv>;
/freebsd/contrib/llvm-project/llvm/lib/AsmParser/
H A DLLLexer.cpp912 INSTKEYWORD(udiv, UDiv); INSTKEYWORD(sdiv, SDiv); INSTKEYWORD(fdiv, FDiv); in LexIdentifier()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.td1384 defm FDIVD : RRFm<"fdiv.d", 0x5D, I64, f64, fdiv>;
1386 defm FDIVS : RRFm<"fdiv.s", 0x5D, F32, f32, fdiv, simm7fp, mimmfp32>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.td1472 [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))],
1477 [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))],
1482 [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>,
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DREADME_P9.txt192 (set f128:$vT, (fdiv f128:$vA, f128:$vB)) // xsdivqp

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