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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFloat.td18 !strconcat("f32.", !strconcat(name, "\t$dst, $src")),
19 !strconcat("f32.", name), f32Inst>;
29 !strconcat("f32.", !strconcat(name, "\t$dst, $lhs, $rhs")),
30 !strconcat("f32.", name), f32Inst>;
39 !strconcat("f32.", !strconcat(name, "\t$dst, $lhs, $rhs")),
40 !strconcat("f32.", name), f32Inst>;
76 def : Pat<(frint f32:$src), (NEAREST_F32 f32:$src)>;
80 def : Pat<(froundeven f32:$src), (NEAREST_F32 f32:$src)>;
93 def : Pat<(seteq f32:$lhs, f32:$rhs), (EQ_F32 f32:$lhs, f32:$rhs)>;
94 def : Pat<(setne f32:$lhs, f32:$rhs), (NE_F32 f32:$lhs, f32:$rhs)>;
[all …]
H A DWebAssemblyInstrMemory.td18 // WebAssembly has i8/i16/i32/i64/f32/f64 memory types, but doesn't have i8/i16
60 defm LOAD_F32 : WebAssemblyLoad<F32, "f32.load", 0x2a, []>;
77 WebAssemblyLoad<F32, "f32.load_f16", 0xfc30, [HasHalfPrecision]>;
97 defm : LoadPat<f32, load, "LOAD_F32">;
118 defm : LoadPat<f32, int_wasm_loadf16_f32, "LOAD_F16_F32">;
145 defm STORE_F32 : WebAssemblyStore<F32, "f32.store", 0x38>;
165 defm : StorePat<f32, store, "STORE_F32">;
177 WebAssemblyStore<F32, "f32.store_f16", 0xfc31, [HasHalfPrecision]>;
185 defm : StorePat<f32, int_wasm_storef16_f32, "STORE_F16_F32">;
H A DWebAssemblyInstrConv.td185 "f32.convert_i32_s\t$dst, $src", "f32.convert_i32_s",
189 "f32.convert_i32_u\t$dst, $src", "f32.convert_i32_u",
201 "f32.convert_i64_s\t$dst, $src", "f32.convert_i64_s",
205 "f32.convert_i64_u\t$dst, $src", "f32.convert_i64_u",
222 "f32.demote_f64\t$dst, $src", "f32.demote_f64",
231 "f32.reinterpret_i32\t$dst, $src",
232 "f32.reinterpret_i32", 0xbe>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DVINTERPInstructions.td68 def VOP3_VINTERP_F32 : VOPProfile<[f32, f32, f32, f32]> {
114 VINTERP_Pseudo <"v_interp_p10_f16_f32", VOP3_VINTERP_F16<[f32, f32, f32, f32]>>;
116 VINTERP_Pseudo <"v_interp_p2_f16_f32", VOP3_VINTERP_F16<[f16, f32, f32, f32]>>;
121 VINTERP_Pseudo <"v_interp_p10_rtz_f16_f32", VOP3_VINTERP_F16<[f32, f32, f32, f32]>>;
123 VINTERP_Pseudo <"v_interp_p2_rtz_f16_f32", VOP3_VINTERP_F16<[f16, f32, f32, f32]>>;
129 (f32 (op
130 (VINTERPMods f32:$src0, i32:$src0_modifiers),
131 (VINTERPMods f32:$src1, i32:$src1_modifiers),
132 (VINTERPMods f32:$src2, i32:$src2_modifiers))),
149 (pat[0] f32:$src0, i32:$src0_modifiers),
[all …]
H A DR600Instructions.td390 SDTypeProfile<1, 8, [SDTCisFP<0>, SDTCisVT<1, f32>, SDTCisVT<2, f32>,
391 SDTCisVT<3, f32>, SDTCisVT<4, f32>, SDTCisVT<5, f32>,
392 SDTCisVT<6, f32>, SDTCisVT<7, f32>, SDTCisVT<8, f32>]>,
685 [(set f32:$dst, (fabs f32
[all...]
H A DR600RegisterInfo.td152 def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
177 def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32,
180 def R600_KC0_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
183 def R600_KC0_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
186 def R600_KC0_W : RegisterClass <"AMDGPU", [f32, i32], 32,
189 def R600_KC0 : RegisterClass <"AMDGPU", [f32, i32], 32,
193 def R600_KC1_X : RegisterClass <"AMDGPU", [f32, i32], 32,
196 def R600_KC1_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
199 def R600_KC1_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
202 def R600_KC1_W : RegisterClass <"AMDGPU", [f32, i32], 32,
[all …]
H A DSIInstructions.td50 [(set f32:$vdst, (int_amdgcn_interp_p1 f32:$vsrc,
77 [(set f32:$vdst, (int_amdgcn_interp_p2 f32:$src0, f32:$vsrc,
87 [(set f32:$vdst, (int_amdgcn_interp_mov (i32 timm:$vsrc),
237 [(set f16:$vdst, (SIfptrunc_round_upward f32:$src0))]>;
241 [(set f16:$vdst, (SIfptrunc_round_downward f32:$src0))]>;
1077 (int_amdgcn_kill (i1 (setcc f32:$src, InlineImmFP32:$imm, cond:$cond))),
1110 (f32 (any_f16_to_fp i32:$src0)),
1115 (f32 (f16_to_fp (and_oneuse i32:$src0, 0x7fff))),
1120 (f32 (f16_to_fp (i32 (srl_oneuse (and_oneuse i32:$src0, 0x7fff0000), (i32 16))))),
1125 (f32 (f16_to_fp (or_oneuse i32:$src0, 0x8000))),
[all …]
H A DAMDGPUCallingConv.td25 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<[
32 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<[
39 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>>
46 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<[
71 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<[
81 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<[
114 CCIfType<[f32, f16, v2f16, bf16, v2bf16] , CCAssignToReg<[
193 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
197 CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1, bf16, v2bf16], CCAssignToReg<[
202 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>>
[all …]
/freebsd/lib/libc/arm/aeabi/
H A Daeabi_vfp_float.S37 vcmp.f32 s0, s1
45 vcmpe.f32 s0, s1
53 vcmpe.f32 s1, s0
61 vcmp.f32 s0, s1
72 vcmp.f32 s0, s1
83 vcmp.f32 s0, s1
94 vcmp.f32 s0, s1
105 vcmp.f32 s0, s1
116 vcmp.f32 s0, s1
133 vcvt.s32.f32 s0, s0
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DVecFuncs.def30 TLI_DEFINE_VECFUNC("llvm.fabs.f32", "vfabsf", FIXED(4), "_ZGV_LLVM_N4v")
33 TLI_DEFINE_VECFUNC("llvm.sqrt.f32", "vsqrtf", FIXED(4), "_ZGV_LLVM_N4v")
37 TLI_DEFINE_VECFUNC("llvm.exp.f32", "vexpf", FIXED(4), "_ZGV_LLVM_N4v")
40 TLI_DEFINE_VECFUNC("llvm.log.f32", "vlogf", FIXED(4), "_ZGV_LLVM_N4v")
43 TLI_DEFINE_VECFUNC("llvm.log10.f32", "vlog10f", FIXED(4), "_ZGV_LLVM_N4v")
48 TLI_DEFINE_VECFUNC("llvm.sin.f32", "vsinf", FIXED(4), "_ZGV_LLVM_N4v")
50 TLI_DEFINE_VECFUNC("llvm.cos.f32", "vcosf", FIXED(4), "_ZGV_LLVM_N4v")
52 TLI_DEFINE_VECFUNC("llvm.tan.f32", "vtanf", FIXED(4), "_ZGV_LLVM_N4v")
72 TLI_DEFINE_VECFUNC("llvm.exp.f32", "_simd_exp_f4", FIXED(4), "_ZGV_LLVM_N4v")
78 TLI_DEFINE_VECFUNC("llvm.acos.f32", "_simd_acos_f4", FIXED(4), "_ZGV_LLVM_N4v")
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.td76 def f32 : VTFP<32, 12>; // 32-bit floating point value
132 def v6i32 : VTVec<6, i32, 62>; // 6 x f32 vector value
133 def v7i32 : VTVec<7, i32, 63>; // 7 x f32 vector value
182 def v1f32 : VTVec<1, f32, 107>; // 1 x f32 vector value
183 def v2f32 : VTVec<2, f32, 108>; // 2 x f32 vector value
184 def v3f32 : VTVec<3, f32, 109>; // 3 x f32 vector value
185 def v4f32 : VTVec<4, f32, 110>; // 4 x f32 vector value
186 def v5f32 : VTVec<5, f32, 111>; // 5 x f32 vector value
187 def v6f32 : VTVec<6, f32, 112>; // 6 x f32 vector value
188 def v7f32 : VTVec<7, f32, 113>; // 7 x f32 vector value
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrVSX.td712 [(set f32:$XT, (fneg (fabs f32:$XB)))]>;
772 [(set f32:$XT, (PPCany_fctidz f32:$XB))]>;
781 [(set f32:$XT, (PPCany_fctiwz f32:$XB))]>;
790 [(set f32:$XT, (PPCany_fctiduz f32:$XB))]>;
799 [(set f32:$XT, (PPCany_fctiwuz f32:$XB))]>;
1032 [(set f32:$XT, (fpimm0))]>;
1123 [(set f32:$XT, (load XForm:$src))]>;
1146 [(store f32:$XT, XForm:$dst)]>;
1159 [(set f32:$XT, (any_fadd f32:$XA, f32:$XB))]>;
1163 [(set f32:$XT, (any_fmul f32:$XA, f32:$XB))]>;
[all …]
H A DPPCInstrSPE.td146 [(set f64:$RT, (any_fpextend f32:$RB))]>;
241 [(set f32:$RT, (fabs f32:$RA))]>;
245 [(set f32:$RT, (any_fadd f32:$RA, f32:$RB))]>;
249 [(set f32:$RT, (any_fpround f64:$RB))]>;
256 [(set f32:$RT, (any_sint_to_fp i32:$RB))]>;
263 [(set f32:$RT, (any_uint_to_fp i32:$RB))]>;
283 [(set i32:$RT, (any_fp_to_sint f32:$RB))]>;
294 [(set i32:$RT, (any_fp_to_uint f32:$RB))]>;
298 [(set f32:$RT, (any_fdiv f32:$RA, f32:$RB))]>;
302 [(set f32:$RT, (any_fmul f32:$RA, f32:$RB))]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYCallingConv.td45 CCIfType<[f32], CCAssignToReg<[R0, R1, R2, R3]>>,
46 CCIfType<[f32], CCAssignToStack<4, 4>>,
57 CCIfType<[f32], CCBitConvertToType<i32>>,
69 CCIfType<[f32], CCAssignToReg<[F0_32, F1_32, F2_32, F3_32]>>,
70 CCIfType<[f32], CCAssignToStack<4, 4>>,
80 CCIfType<[f32], CCAssignToReg<[F0_32]>>,
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsNVVM.td32 // * llvm.nvvm.h2f --> llvm.convert.to.fp16.f32
59 !eq(gft,"m16n8k8:c:f32") : !listsplat(llvm_float_ty, 4),
60 !eq(gft,"m16n8k8:d:f32") : !listsplat(llvm_float_ty, 4),
65 !eq(gft,"m16n8k16:c:f32") : !listsplat(llvm_float_ty, 4),
66 !eq(gft,"m16n8k16:d:f32") : !listsplat(llvm_float_ty, 4),
67 !eq(gft,"m16n8k4:c:f32") : !listsplat(llvm_float_ty, 4),
68 !eq(gft,"m16n8k4:d:f32") : !listsplat(llvm_float_ty, 4),
71 // All other supported geometries use the same fragment format for f32 and
77 !eq(ft,"c:f32") : !listsplat(llvm_float_ty, 8),
78 !eq(ft,"d:f32") : !listsplat(llvm_float_ty, 8),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXIntrinsics.td163 !eq(reg, "f32"): Float32Regs);
200 foreach regclass = ["i32", "f32"] in {
653 def INT_NVVM_FMIN_F : F_MATH_2<"min.f32 \t$dst, $src0, $src1;", Float32Regs,
655 def INT_NVVM_FMIN_FTZ_F : F_MATH_2<"min.ftz.f32 \t$dst, $src0, $src1;",
657 def INT_NVVM_FMIN_NAN_F : F_MATH_2<"min.NaN.f32 \t$dst, $src0, $src1;",
660 def INT_NVVM_FMIN_FTZ_NAN_F : F_MATH_2<"min.ftz.NaN.f32 \t$dst, $src0, $src1;",
664 F_MATH_2<"min.xorsign.abs.f32 \t$dst, $src0, $src1;",
668 F_MATH_2<"min.ftz.xorsign.abs.f32 \t$dst, $src0, $src1;",
672 F_MATH_2<"min.NaN.xorsign.abs.f32 \t$dst, $src0, $src1;",
676 F_MATH_2<"min.ftz.NaN.xorsign.abs.f32 \t$dst, $src0, $src1;",
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td18 : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i64>]>;
20 : SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, f32>]>;
265 defm : LdPat<load, FLD_S, f32>;
266 def : RegRegLdPat<load, FLDX_S, f32>;
270 defm : StPat<store, FST_S, FPR32, f32>;
271 def : RegRegStPat<store, FSTX_S, FPR32, f32>;
275 def : Pat<(f32 fpimm0), (MOVGR2FR_W R0)>;
276 def : Pat<(f32 fpimm0neg), (FNEG_S (MOVGR2FR_W R0))>;
277 def : Pat<(f32 fpimm1), (FFINT_S_W (MOVGR2FR_W (ADDI_W R0, 1)))>;
321 // int -> f32
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrCDE.td548 def : Pat<(f32 (int_arm_cde_vcx1 timm:$coproc, timm:$imm)),
549 (f32 (CDE_VCX1_fpsp p_imm:$coproc, imm_11b:$imm))>;
550 def : Pat<(f32 (int_arm_cde_vcx1a timm:$coproc, (f32 SPR:$acc), timm:$imm)),
551 (f32 (CDE_VCX1A_fpsp p_imm:$coproc, SPR:$acc, imm_11b:$imm))>;
557 def : Pat<(f32 (int_arm_cde_vcx2 timm:$coproc, (f32 SPR:$n), timm:$imm)),
558 (f32 (CDE_VCX2_fpsp p_imm:$coproc, SPR:$n, imm_6b:$imm))>;
559 def : Pat<(f32 (int_arm_cde_vcx2a timm:$coproc, (f32 SPR:$acc), (f32 SPR:$n),
561 (f32 (CDE_VCX2A_fpsp p_imm:$coproc, SPR:$acc, SPR:$n, imm_6b:$imm))>;
568 def : Pat<(f32 (int_arm_cde_vcx3 timm:$coproc, (f32 SPR:$n), (f32 SPR:$m),
570 (f32 (CDE_VCX3_fpsp p_imm:$coproc, (f32 SPR:$n), (f32 SPR:$m),
[all …]
H A DARMInstrVFP.td19 def SDT_VMOVSR : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i32>]>;
63 def vfp_f32f16imm : PatLeaf<(f32 fpimm), [{
76 def vfp_f32imm : Operand<f32>,
77 PatLeaf<(f32 fpimm), [{
435 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
460 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
485 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
506 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
531 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
557 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallingConv.td86 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
104 // f32 are returned in registers F0, F2
105 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
151 // f32 arguments are passed in single precision FP registers.
152 CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15,
164 CCIfType<[f32], CCAssignToStack<4, 8>>,
178 CCIfType<[f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
184 CCIfType<[f32], CCAssignToStack<4, 8>>,
189 // f128 needs to be handled similarly to f32 and f64. However, f128 is not
213 // f32 are returned in registers F0, F2
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZfbfmin.td21 : SDTypeProfile<1, 1, [SDTCisVT<0, bf16>, SDTCisVT<1, f32>]>;
23 : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, bf16>]>;
53 // f32 -> bf16, bf16 -> f32
66 // bf16->[u]int. Round-to-zero must be used for the f32->int step, the
67 // rounding mode has no effect for bf16->f32.
77 // bf16->[u]int64. Round-to-zero must be used for the f32->int step, the
78 // rounding mode has no effect for bf16->f32.
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcCallingConv.td20 // i32 f32 arguments get passed in integer registers if there is space.
21 CCIfType<[i32, f32], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>,
35 CCIfType<[f32], CCAssignToReg<[F0, F1, F2, F3]>>,
115 CCIfInReg<CCIfType<[i32, f32], CCCustom<"CC_Sparc64_Half">>>,
126 // A single f32 return value always goes in %f0. The ABI doesn't specify what
127 // happens to multiple f32 return values outside a struct.
128 CCIfType<[f32], CCCustom<"RetCC_Sparc64_Half">>,
133 CCIfInReg<CCIfType<[i32, f32], CCCustom<"RetCC_Sparc64_Half">>>,
/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/arm/
H A Dextendsfdf2vfp.S22 vcvt.f64.f32 d0, s0
25 vcvt.f64.f32 d7, s15 // convert single to double
H A Dtruncdfsf2vfp.S22 vcvt.f32.f64 s0, d0
25 vcvt.f32.f64 s15, d7 // convert double to single (trucate precision)
H A Daddsf3vfp.S21 vadd.f32 s0, s0, s1
25 vadd.f32 s14, s14, s15

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