Searched refs:esr_iss (Results 1 – 2 of 2) sorted by relevance
599 arm64_gen_inst_emul_data(struct hypctx *hypctx, uint32_t esr_iss, in arm64_gen_inst_emul_data() argument615 esr_sas = (esr_iss & ISS_DATA_SAS_MASK) >> ISS_DATA_SAS_SHIFT; in arm64_gen_inst_emul_data()616 reg_num = (esr_iss & ISS_DATA_SRT_MASK) >> ISS_DATA_SRT_SHIFT; in arm64_gen_inst_emul_data()620 vie->sign_extend = (esr_iss & ISS_DATA_SSE) ? 1 : 0; in arm64_gen_inst_emul_data()621 vie->dir = (esr_iss & ISS_DATA_WnR) ? VM_DIR_WRITE : VM_DIR_READ; in arm64_gen_inst_emul_data()635 arm64_gen_reg_emul_data(uint32_t esr_iss, struct vm_exit *vme_ret) in arm64_gen_reg_emul_data() argument643 vre->inst_syndrome = esr_iss; in arm64_gen_reg_emul_data()645 vre->dir = (esr_iss & ISS_MSR_DIR) ? VM_DIR_READ : VM_DIR_WRITE; in arm64_gen_reg_emul_data()646 reg_num = ISS_MSR_Rt(esr_iss); in arm64_gen_reg_emul_data()673 uint32_t esr_ec, esr_iss; in handle_el1_sync_excp() local[all …]
107 uint32_t esr_iss; member639 .esr_iss = ((_reg ## _op0) << ISS_MSR_OP0_SHIFT) | \651 .esr_iss = ((_reg ## _op0) << ISS_MSR_OP0_SHIFT) | \674 .esr_iss = (3 << ISS_MSR_OP0_SHIFT) |702 if (vm->special_reg[i].esr_iss == 0 && in vm_register_reg_handler()704 vm->special_reg[i].esr_iss = iss; in vm_register_reg_handler()722 if (vm->special_reg[i].esr_iss == iss && in vm_deregister_reg_handler()747 if (vm->special_reg[i].esr_iss == 0 && in vm_handle_reg_emul()752 vm->special_reg[i].esr_iss) { in vm_handle_reg_emul()765 vmm_special_regs[i].esr_iss) { in vm_handle_reg_emul()