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Searched refs:csr (Results 1 – 25 of 98) sorted by relevance

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/freebsd/sys/dev/qat/qat_api/firmware/include/
H A Dicp_qat_hw_20_comp.h59 ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(icp_qat_hw_comp_20_config_csr_lower_t csr) in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER() argument
64 csr.algo, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
69 csr.sd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
75 csr.edmm, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
80 csr.hbs, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
85 csr.mmctrl, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
90 csr.hash_col, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
95 csr.hash_update, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
100 csr.skip_ctrl, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
106 csr.abd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
[all …]
/freebsd/sys/powerpc/booke/
H A Dmachdep_e500.c56 uint32_t csr; in booke_enable_l1_cache() local
59 csr = mfspr(SPR_L1CSR0); in booke_enable_l1_cache()
60 if ((csr & L1CSR0_DCE) == 0) { in booke_enable_l1_cache()
65 csr = mfspr(SPR_L1CSR0); in booke_enable_l1_cache()
66 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0) in booke_enable_l1_cache()
68 (csr & L1CSR0_DCE) ? "en" : "dis"); in booke_enable_l1_cache()
71 csr = mfspr(SPR_L1CSR1); in booke_enable_l1_cache()
72 if ((csr & L1CSR1_ICE) == 0) { in booke_enable_l1_cache()
77 csr = mfspr(SPR_L1CSR1); in booke_enable_l1_cache()
78 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0) in booke_enable_l1_cache()
[all …]
H A Dmp_cpudep.c53 uint32_t msr, csr; in cpudep_ap_bootstrap() local
57 csr = mfspr(SPR_L1CSR0); in cpudep_ap_bootstrap()
58 if ((csr & L1CSR0_DCE) == 0) { in cpudep_ap_bootstrap()
63 csr = mfspr(SPR_L1CSR1); in cpudep_ap_bootstrap()
64 if ((csr & L1CSR1_ICE) == 0) { in cpudep_ap_bootstrap()
/freebsd/sys/dev/qat/include/common/
H A Dicp_qat_hal.h144 #define CAP_CSR_ADDR(csr) (csr + handle->hal_cap_g_ctl_csr_addr_v) argument
145 #define SET_CAP_CSR(handle, csr, val) \ argument
146 ADF_CSR_WR(handle->hal_misc_addr_v, CAP_CSR_ADDR(csr), val)
147 #define GET_CAP_CSR(handle, csr) \ argument
148 ADF_CSR_RD(handle->hal_misc_addr_v, CAP_CSR_ADDR(csr))
149 #define SET_GLB_CSR(handle, csr, val) \ argument
153 SET_CAP_CSR((handle), (csr), (val)) : \
154 SET_CAP_CSR((handle), (csr) + GLOBAL_CSR, val); \
156 #define GET_GLB_CSR(handle, csr) \ argument
160 GET_CAP_CSR((handle), (csr)) : \
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_200xx/
H A Dadf_200xx_hw_data.c178 adf_enable_error_interrupts(struct resource *csr) in adf_enable_error_interrupts() argument
180 ADF_CSR_WR(csr, ADF_ERRMSK0, ADF_200XX_ERRMSK0_CERR); /* ME0-ME3 */ in adf_enable_error_interrupts()
181 ADF_CSR_WR(csr, ADF_ERRMSK1, ADF_200XX_ERRMSK1_CERR); /* ME4-ME5 */ in adf_enable_error_interrupts()
182 ADF_CSR_WR(csr, ADF_ERRMSK5, ADF_200XX_ERRMSK5_CERR); /* SSM2 */ in adf_enable_error_interrupts()
185 adf_csr_fetch_and_and(csr, ADF_ERRMSK3, ADF_200XX_VF2PF1_16); in adf_enable_error_interrupts()
188 ADF_CSR_WR(csr, ADF_200XX_RICPPINTCTL, ADF_200XX_RICPP_EN); in adf_enable_error_interrupts()
191 ADF_CSR_WR(csr, ADF_200XX_TICPPINTCTL, ADF_200XX_TICPP_EN); in adf_enable_error_interrupts()
194 ADF_CSR_WR(csr, ADF_200XX_CPP_CFC_ERR_CTRL, ADF_200XX_CPP_CFC_UE); in adf_enable_error_interrupts()
201 struct resource *csr = misc_bar->virt_addr; in adf_disable_error_interrupts() local
204 ADF_CSR_WR(csr, in adf_disable_error_interrupts()
[all …]
/freebsd/sys/riscv/include/
H A Driscvreg.h229 #define csr_swap(csr, val) \ argument
232 __asm __volatile("csrrwi %0, " #csr ", %1" \
235 __asm __volatile("csrrw %0, " #csr ", %1" \
240 #define csr_write(csr, val) \ argument
242 __asm __volatile("csrwi " #csr ", %0" :: "i" (val)); \
244 __asm __volatile("csrw " #csr ", %0" :: "r" (val)); \
247 #define csr_set(csr, val) \ argument
249 __asm __volatile("csrsi " #csr ", %0" :: "i" (val)); \
251 __asm __volatile("csrs " #csr ", %0" :: "r" (val)); \
254 #define csr_clear(csr, val) \ argument
[all …]
/freebsd/sys/dev/usb/controller/
H A Dmusb_otg.c403 uint8_t csr; in musbotg_dev_ctrl_setup_rx() local
421 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); in musbotg_dev_ctrl_setup_rx()
423 DPRINTFN(4, "csr=0x%02x\n", csr); in musbotg_dev_ctrl_setup_rx()
429 if (csr & MUSB2_MASK_CSR0L_DATAEND) { in musbotg_dev_ctrl_setup_rx()
437 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { in musbotg_dev_ctrl_setup_rx()
441 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); in musbotg_dev_ctrl_setup_rx()
445 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { in musbotg_dev_ctrl_setup_rx()
450 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); in musbotg_dev_ctrl_setup_rx()
458 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { in musbotg_dev_ctrl_setup_rx()
529 uint8_t csr, csrh; in musbotg_host_ctrl_setup_tx() local
[all …]
/freebsd/sys/dev/qat/qat_common/
H A Dadf_hw_arbiter.c53 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_arb() local
63 WRITE_CSR_ARB_SARCONFIG(csr, info.arbiter_offset, arb, arb_cfg); in adf_init_arb()
73 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_gen2_arb() local
88 WRITE_CSR_ARB_WRK_2_SER_MAP(csr, in adf_init_gen2_arb()
162 struct resource *csr = csr_addr; in adf_disable_ring_arb() local
169 arbenable = csr_ops->read_csr_ring_srv_arb_en(csr, bank_nr); in adf_disable_ring_arb()
171 csr_ops->write_csr_ring_srv_arb_en(csr, bank_nr, arbenable); in adf_disable_ring_arb()
181 struct resource *csr; in adf_exit_arb() local
187 csr = accel_dev->transport->banks[0].csr_addr; in adf_exit_arb()
193 WRITE_CSR_ARB_SARCONFIG(csr, info.arbiter_offset, i, 0); in adf_exit_arb()
[all …]
H A Dadf_dev_err.c178 struct resource *csr = misc_bar->virt_addr; in adf_print_err_registers() local
184 val = ADF_CSR_RD(csr, adf_err_regs[i].offs); in adf_print_err_registers()
196 val = adf_accel_err_regs[i].read(csr, accel); in adf_print_err_registers()
224 struct resource *csr, in adf_handle_slice_hang() argument
227 u32 slice_hang = ADF_CSR_RD(csr, slice_hang_offset); in adf_handle_slice_hang()
264 ADF_CSR_WR(csr, slice_hang_offset, slice_hang); in adf_handle_slice_hang()
280 struct resource *csr = misc_bar->virt_addr; in adf_check_slice_hang() local
281 u32 errsou3 = ADF_CSR_RD(csr, ADF_ERRSOU3); in adf_check_slice_hang()
282 u32 errsou5 = ADF_CSR_RD(csr, ADF_ERRSOU5); in adf_check_slice_hang()
306 if (ADF_CSR_RD(csr, ADF_INTSTATSSM(accel_num)) & in adf_check_slice_hang()
[all …]
H A Dadf_freebsd_transport_debug.c23 struct resource *csr = ring->bank->csr_addr; in adf_ring_show() local
32 head = csr_ops->read_csr_ring_head(csr, in adf_ring_show()
35 tail = csr_ops->read_csr_ring_tail(csr, in adf_ring_show()
38 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number); in adf_ring_show()
139 struct resource *csr = bank->csr_addr; in adf_bank_show() local
145 head = csr_ops->read_csr_ring_head(csr, in adf_bank_show()
148 tail = csr_ops->read_csr_ring_tail(csr, in adf_bank_show()
151 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number); in adf_bank_show()
H A Dqat_hal.c112 unsigned int csr, in qat_hal_rd_ae_csr() argument
118 *value = GET_AE_CSR(handle, ae, csr); in qat_hal_rd_ae_csr()
130 unsigned int csr, in qat_hal_wr_ae_csr() argument
136 SET_AE_CSR(handle, ae, csr, value); in qat_hal_wr_ae_csr()
166 unsigned int csr = (1 << ACS_ABO_BITPOS); in qat_hal_wait_cycles() local
174 qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &csr); in qat_hal_wait_cycles()
184 if (elapsed_cycles >= 8 && !(csr & (1 << ACS_ABO_BITPOS))) in qat_hal_wait_cycles()
208 unsigned int csr, new_csr; in qat_hal_set_ae_ctx_mode() local
216 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr); in qat_hal_set_ae_ctx_mode()
217 csr = IGNORE_W1C_MASK & csr; in qat_hal_set_ae_ctx_mode()
[all …]
H A Dadf_gen4_hw_data.c154 reset_ring_pair(struct resource *csr, u32 bank_number) in reset_ring_pair() argument
166 ADF_CSR_WR(csr, in reset_ring_pair()
172 val = ADF_CSR_RD(csr, ADF_WQM_CSR_RPRESETSTS(bank_number)); in reset_ring_pair()
182 ADF_CSR_WR(csr, in reset_ring_pair()
193 struct resource *csr; in adf_gen4_ring_pair_reset() local
199 csr = (&GET_BARS(accel_dev)[etr_bar_id])->virt_addr; in adf_gen4_ring_pair_reset()
201 ret = reset_ring_pair(csr, bank_number); in adf_gen4_ring_pair_reset()
/freebsd/crypto/openssl/test/certs/
H A Dmkcert.sh113 csr=$(req "$key" "CN = $cn") || return 1
114 echo "$csr" |
154 csr=$(req "$key" "CN = $cn") || return 1
155 echo "$csr" |
175 csr=$(req "$key" "CN = $cn") || return 1
176 echo "$csr" |
264 csr=$(req "$key" "CN = $cn") || return 1
265 echo "$csr" |
298 csr=$(req "$key" "CN = $cn") || return 1
299 echo "$csr" |
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_res_part.c64 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_enable_sym_threads() local
73 WRITE_CSR_WQM(csr, in adf_enable_sym_threads()
82 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_enable_asym_threads() local
93 WRITE_CSR_WQM(csr, in adf_enable_asym_threads()
102 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_enable_dc_threads() local
111 WRITE_CSR_WQM(csr, in adf_enable_dc_threads()
125 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_arb_c4xxx() local
136 WRITE_CSR_WQM(csr, in adf_init_arb_c4xxx()
170 struct resource *csr; in adf_exit_arb_c4xxx() local
176 csr = accel_dev->transport->banks[0].csr_addr; in adf_exit_arb_c4xxx()
[all …]
H A Dadf_c4xxx_hw_data.c209 struct resource *csr = misc_bar->virt_addr; in c4xxx_set_ssm_wdtimer() local
228 ADF_CSR_WR(csr, ADF_C4XXX_SSMWDTL_OFFSET(accel), ssm_wdt_low); in c4xxx_set_ssm_wdtimer()
229 ADF_CSR_WR(csr, ADF_C4XXX_SSMWDTH_OFFSET(accel), ssm_wdt_high); in c4xxx_set_ssm_wdtimer()
230 ADF_CSR_WR(csr, in c4xxx_set_ssm_wdtimer()
233 ADF_CSR_WR(csr, in c4xxx_set_ssm_wdtimer()
252 struct resource *csr = misc_bar->virt_addr; in c4xxx_check_slice_hang() local
259 u32 errsou10 = ADF_CSR_RD(csr, ADF_C4XXX_ERRSOU10); in c4xxx_check_slice_hang()
269 fw_irq_source = ADF_CSR_RD(csr, ADF_INTSTATSSM(accel_num)); in c4xxx_check_slice_hang()
271 ADF_CSR_RD(csr, ADF_C4XXX_IAINTSTATSSM(accel_num)); in c4xxx_check_slice_hang()
284 adf_csr_fetch_and_and(csr, slice_hang_offset, ~0); in c4xxx_check_slice_hang()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/apm/
H A Dapm-storm.dtsi196 reg-names = "csr-reg", "div-reg";
197 csr-offset = <0x0>;
198 csr-mask = <0x2>;
225 reg-names = "csr-reg";
234 reg-names = "csr-reg";
235 csr-mask = <0xa>;
245 reg-names = "csr-reg";
246 csr-mask = <0x3>;
256 reg-names = "csr-reg";
257 csr-mask = <0x3>;
[all …]
/freebsd/crypto/openssl/test/testutil/
H A Dload.c94 X509_REQ *csr = NULL; in load_csr_der() local
100 csr = X509_REQ_new_ex(libctx, NULL); in load_csr_der()
101 if (TEST_ptr(csr)) in load_csr_der()
102 (void)TEST_ptr(d2i_X509_REQ_bio(bio, &csr)); in load_csr_der()
104 return csr; in load_csr_der()
/freebsd/sys/dev/iicbus/rtc/
H A Dnxprtc.c441 struct csr { in pcf8523_start() struct
446 } csr; in pcf8523_start() local
451 if ((err = nxprtc_readfrom(sc->dev, PCF85xx_R_CS1, &csr, in pcf8523_start()
452 sizeof(csr), WAITFLAGS)) != 0){ in pcf8523_start()
463 if ((csr.cs3 & PCF8523_M_CS3_PM) == PCF8523_B_CS3_PM_NOBAT || in pcf8523_start()
464 (csr.cs1 & PCF85xx_B_CS1_STOP) || (csr.sec & PCF85xx_B_SECOND_OS)) { in pcf8523_start()
529 if (csr.cs1 & PCF2129_B_CS1_12HR) in pcf8523_start()
547 if (csr.cs1 & PCF8523_B_CS1_12HR) in pcf8523_start()
615 struct csr { in pcf8563_start() struct
619 } csr; in pcf8563_start() local
[all …]
/freebsd/contrib/wpa/src/crypto/
H A Dcrypto_wolfssl.c3233 static void crypto_csr_init_type(struct crypto_csr *csr, enum cert_type type, in crypto_csr_init_type() argument
3238 if (csr->type == type) in crypto_csr_init_type()
3241 switch (csr->type) { in crypto_csr_init_type()
3243 wc_FreeDecodedCert(&csr->req.dc); in crypto_csr_init_type()
3247 wc_SetCert_Free(&csr->req.c); in crypto_csr_init_type()
3256 wc_InitDecodedCert(&csr->req.dc, source, in_sz, NULL); in crypto_csr_init_type()
3259 err = wc_InitCert(&csr->req.c); in crypto_csr_init_type()
3267 csr->type = type; in crypto_csr_init_type()
3288 void crypto_csr_deinit(struct crypto_csr *csr) in crypto_csr_deinit() argument
3290 if (csr) { in crypto_csr_deinit()
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_dh895xcc/
H A Dadf_dh895xcc_hw_data.c198 struct resource *csr = misc_bar->virt_addr; in adf_enable_error_correction() local
207 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i)); in adf_enable_error_correction()
209 ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val); in adf_enable_error_correction()
210 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_MISC_CONTROL(i)); in adf_enable_error_correction()
212 ADF_CSR_WR(csr, ADF_DH895XCC_AE_MISC_CONTROL(i), val); in adf_enable_error_correction()
220 val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i)); in adf_enable_error_correction()
222 ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val); in adf_enable_error_correction()
223 val = ADF_CSR_RD(csr, ADF_DH895XCC_CERRSSMSH(i)); in adf_enable_error_correction()
225 ADF_CSR_WR(csr, ADF_DH895XCC_CERRSSMSH(i), val); in adf_enable_error_correction()
/freebsd/sys/dev/qat/qat_hw/qat_c3xxx/
H A Dadf_c3xxx_hw_data.c181 struct resource *csr = misc_bar->virt_addr; in adf_enable_error_correction() local
190 val = ADF_CSR_RD(csr, ADF_C3XXX_AE_CTX_ENABLES(i)); in adf_enable_error_correction()
192 ADF_CSR_WR(csr, ADF_C3XXX_AE_CTX_ENABLES(i), val); in adf_enable_error_correction()
193 val = ADF_CSR_RD(csr, ADF_C3XXX_AE_MISC_CONTROL(i)); in adf_enable_error_correction()
195 ADF_CSR_WR(csr, ADF_C3XXX_AE_MISC_CONTROL(i), val); in adf_enable_error_correction()
203 val = ADF_CSR_RD(csr, ADF_C3XXX_UERRSSMSH(i)); in adf_enable_error_correction()
205 ADF_CSR_WR(csr, ADF_C3XXX_UERRSSMSH(i), val); in adf_enable_error_correction()
206 val = ADF_CSR_RD(csr, ADF_C3XXX_CERRSSMSH(i)); in adf_enable_error_correction()
208 ADF_CSR_WR(csr, ADF_C3XXX_CERRSSMSH(i), val); in adf_enable_error_correction()
/freebsd/sys/dev/qat/qat_hw/qat_c62x/
H A Dadf_c62x_hw_data.c185 struct resource *csr = misc_bar->virt_addr; in adf_enable_error_correction() local
194 val = ADF_CSR_RD(csr, ADF_C62X_AE_CTX_ENABLES(i)); in adf_enable_error_correction()
196 ADF_CSR_WR(csr, ADF_C62X_AE_CTX_ENABLES(i), val); in adf_enable_error_correction()
197 val = ADF_CSR_RD(csr, ADF_C62X_AE_MISC_CONTROL(i)); in adf_enable_error_correction()
199 ADF_CSR_WR(csr, ADF_C62X_AE_MISC_CONTROL(i), val); in adf_enable_error_correction()
207 val = ADF_CSR_RD(csr, ADF_C62X_UERRSSMSH(i)); in adf_enable_error_correction()
209 ADF_CSR_WR(csr, ADF_C62X_UERRSSMSH(i), val); in adf_enable_error_correction()
210 val = ADF_CSR_RD(csr, ADF_C62X_CERRSSMSH(i)); in adf_enable_error_correction()
212 ADF_CSR_WR(csr, ADF_C62X_CERRSSMSH(i), val); in adf_enable_error_correction()
/freebsd/sys/powerpc/mpc85xx/
H A Dmpc85xx.c294 uint32_t csr, size, ver; in mpc85xx_enable_l3_cache() local
300 csr = ccsr_read4(OCP85XX_CPC_CSR0); in mpc85xx_enable_l3_cache()
301 if ((csr & OCP85XX_CPC_CSR0_CE) == 0) { in mpc85xx_enable_l3_cache()
306 csr = ccsr_read4(OCP85XX_CPC_CSR0); in mpc85xx_enable_l3_cache()
308 (csr & OCP85XX_CPC_CSR0_CE) == 0) { in mpc85xx_enable_l3_cache()
311 size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ? in mpc85xx_enable_l3_cache()
/freebsd/sys/dev/mii/
H A Dlxtphy.c194 int bmcr, bmsr, csr; in lxtphy_status() local
204 csr = PHY_READ(sc, MII_LXTPHY_CSR); in lxtphy_status()
205 if (csr & CSR_LINK) in lxtphy_status()
225 if (csr & CSR_SPEED) in lxtphy_status()
229 if (csr & CSR_DUPLEX) in lxtphy_status()
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dxgene.txt40 may include "csr-reg" and/or "div-reg". If this property
42 only "csr-reg".
49 - csr-offset : Offset to the CSR reset register from the reset address base.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
96 reg-name = "csr-reg";
120 reg-names = "csr-reg", "div-reg";
121 csr-offset = <0x0>;
122 csr-mask = <0x200>;

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