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Searched refs:createRegister (Results 1 – 15 of 15) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUArgumentUsageInfo.cpp157 = ArgDescriptor::createRegister(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3); in fixedABILayout()
158 AI.DispatchPtr = ArgDescriptor::createRegister(AMDGPU::SGPR4_SGPR5); in fixedABILayout()
159 AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::SGPR6_SGPR7); in fixedABILayout()
163 AI.ImplicitArgPtr = ArgDescriptor::createRegister(AMDGPU::SGPR8_SGPR9); in fixedABILayout()
164 AI.DispatchID = ArgDescriptor::createRegister(AMDGPU::SGPR10_SGPR11); in fixedABILayout()
167 AI.WorkGroupIDX = ArgDescriptor::createRegister(AMDGPU::SGPR12); in fixedABILayout()
168 AI.WorkGroupIDY = ArgDescriptor::createRegister(AMDGPU::SGPR13); in fixedABILayout()
169 AI.WorkGroupIDZ = ArgDescriptor::createRegister(AMDGPU::SGPR14); in fixedABILayout()
170 AI.LDSKernelId = ArgDescriptor::createRegister(AMDGPU::SGPR15); in fixedABILayout()
173 AI.WorkItemIDX = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask); in fixedABILayout()
[all …]
H A DSIMachineFunctionInfo.cpp88 ArgDescriptor::createRegister(ScratchRSrcReg); in SIMachineFunctionInfo()
104 ArgDescriptor::createRegister(ScratchRSrcReg); in SIMachineFunctionInfo()
157 ArgDescriptor::createRegister(AMDGPU::SGPR5); in SIMachineFunctionInfo()
199 ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addPrivateSegmentBuffer()
206 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchPtr()
213 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addQueuePtr()
221 = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addKernargSegmentPtr()
228 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchID()
235 ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addFlatScratchInit()
242 ArgInfo.PrivateSegmentSize = ArgDescriptor::createRegister(getNextUserSGPR()); in addPrivateSegmentSize()
[all …]
H A DSIMachineFunctionInfo.h863 ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
869 ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
875 ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
881 ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
903 = ArgDescriptor::createRegister(getNextSystemSGPR());
909 ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
H A DAMDGPUArgumentUsageInfo.h46 static ArgDescriptor createRegister(Register Reg, unsigned Mask = ~0u) {
H A DSIISelLowering.cpp2247 ArgDescriptor::createRegister(AMDGPU::TTMP9); in getPreloadedValue()
2251 const ArgDescriptor WorkGroupIDY = ArgDescriptor::createRegister( in getPreloadedValue()
2255 ArgDescriptor::createRegister(AMDGPU::TTMP7, 0xFFFF0000u); in getPreloadedValue()
2358 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg, Mask)); in allocateSpecialEntryInputVGPRs()
2365 ArgDescriptor::createRegister(AMDGPU::VGPR0, 0x3ff << 10)); in allocateSpecialEntryInputVGPRs()
2371 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg)); in allocateSpecialEntryInputVGPRs()
2379 ArgDescriptor::createRegister(AMDGPU::VGPR0, 0x3ff << 20)); in allocateSpecialEntryInputVGPRs()
2385 Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg)); in allocateSpecialEntryInputVGPRs()
2415 return ArgDescriptor::createRegister(Reg, Mask); in allocateVGPR32Input()
2432 return ArgDescriptor::createRegister(Reg); in allocateSGPR32InputImpl()
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H A DAMDGPUTargetMachine.cpp1902 Arg = ArgDescriptor::createRegister(Reg); in parseMachineFunctionInfo()
H A DAMDGPULegalizerInfo.cpp4359 ArgDescriptor::createRegister(AMDGPU::TTMP9); in loadInputValue()
4363 const ArgDescriptor WorkGroupIDY = ArgDescriptor::createRegister( in loadInputValue()
4367 ArgDescriptor::createRegister(AMDGPU::TTMP7, 0xFFFF0000u); in loadInputValue()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfExpression.cpp105 DwarfRegs.push_back(Register::createRegister(-1, nullptr)); in addMachineReg()
111 DwarfRegs.push_back(Register::createRegister(Reg, nullptr)); in addMachineReg()
121 DwarfRegs.push_back(Register::createRegister(Reg, nullptr)); in addMachineReg()
133 DwarfRegs.push_back(Register::createRegister(Reg, "super-register")); in addMachineReg()
173 DwarfRegs.push_back(Register::createRegister(Reg, "sub-register")); in addMachineReg()
H A DDwarfExpression.h53 static Register createRegister(int64_t RegNo, const char *Comment) { in createRegister() function
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCFIInstBuilder.h92 insertCFIInst(MCCFIInstruction::createRegister( in buildRegister()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCFIInstrInserter.cpp401 MCCFIInstruction::createRegister(nullptr, Reg, *RO.Reg)); in insertCFIInstrs()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCDwarf.h642 static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1,
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCStreamer.cpp655 MCCFIInstruction::createRegister(Label, Register1, Register2, Loc); in emitCFIRegister()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp1216 unsigned CFIRegister = MF.addFrameInst(MCCFIInstruction::createRegister( in emitPrologue()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp2599 MF.addFrameInst(MCCFIInstruction::createRegister(nullptr, Reg, Reg2)); in parseCFIOperand()