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Searched refs:createQTuple (Results 1 – 2 of 2) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp351 SDValue createQTuple(ArrayRef<SDValue> Vecs);
1406 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() function in AArch64DAGToDAGISel
1477 SDValue RegSeq = createQTuple(Regs); in SelectTable()
2176 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore()
2240 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore()
2299 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane()
2337 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane()
2391 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane()
2419 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp732 static Register createQTuple(ArrayRef<Register> Regs, MachineIRBuilder &MIB) { in createQTuple() function
5134 auto RegSeq = createQTuple(Regs, MIB); in selectShuffleVector()
5906 Register Tuple = createQTuple(Regs, MIB); in selectVectorLoadLaneIntrinsic()
5947 Register Tuple = Ty.getSizeInBits() == 128 ? createQTuple(Regs, MIB) in selectVectorStoreIntrinsic()
5971 Register Tuple = createQTuple(Regs, MIB); in selectVectorStoreLaneIntrinsic()
6862 Register RegSeq = createQTuple(Regs, MIB); in SelectTable()