1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2003-2008 Joseph Koshy
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/types.h>
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/pmc.h>
33 #include <sys/syscall.h>
34
35 #if defined(__amd64__) || defined(__i386__)
36 #include <machine/cpufunc.h>
37 #endif
38
39 #include <ctype.h>
40 #include <errno.h>
41 #include <err.h>
42 #include <fcntl.h>
43 #include <pmc.h>
44 #include <stdio.h>
45 #include <stdlib.h>
46 #include <string.h>
47 #include <strings.h>
48 #include <sysexits.h>
49 #include <unistd.h>
50
51 #include "libpmcinternal.h"
52
53 /* Function prototypes */
54 #if defined(__amd64__) || defined(__i386__)
55 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
56 struct pmc_op_pmcallocate *_pmc_config);
57 static int ibs_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
58 struct pmc_op_pmcallocate *_pmc_config);
59 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
60 struct pmc_op_pmcallocate *_pmc_config);
61 static int rapl_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
62 struct pmc_op_pmcallocate *_pmc_config);
63 #endif
64 #if defined(__arm__)
65 static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
66 struct pmc_op_pmcallocate *_pmc_config);
67 #endif
68 #if defined(__aarch64__)
69 static int arm64_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
70 struct pmc_op_pmcallocate *_pmc_config);
71 static int cmn600_pmu_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
72 struct pmc_op_pmcallocate *_pmc_config);
73 static int dmc620_pmu_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
74 struct pmc_op_pmcallocate *_pmc_config);
75 #endif
76 static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
77 struct pmc_op_pmcallocate *_pmc_config);
78
79 #if defined(__powerpc__)
80 static int powerpc_allocate_pmc(enum pmc_event _pe, char* ctrspec,
81 struct pmc_op_pmcallocate *_pmc_config);
82 #endif /* __powerpc__ */
83
84 #define PMC_CALL(op, params) syscall(pmc_syscall, (op), (params))
85
86 /*
87 * Event aliases provide a way for the user to ask for generic events
88 * like "cache-misses", or "instructions-retired". These aliases are
89 * mapped to the appropriate canonical event descriptions using a
90 * lookup table.
91 */
92 struct pmc_event_alias {
93 const char *pm_alias;
94 const char *pm_spec;
95 };
96
97 static const struct pmc_event_alias *pmc_mdep_event_aliases;
98
99 /*
100 * The pmc_event_descr structure maps symbolic names known to the user
101 * to integer codes used by the PMC KLD.
102 */
103 struct pmc_event_descr {
104 const char *pm_ev_name;
105 enum pmc_event pm_ev_code;
106 };
107
108 /*
109 * The pmc_class_descr structure maps class name prefixes for
110 * event names to event tables and other PMC class data.
111 */
112 struct pmc_class_descr {
113 const char *pm_evc_name;
114 size_t pm_evc_name_size;
115 enum pmc_class pm_evc_class;
116 const struct pmc_event_descr *pm_evc_event_table;
117 size_t pm_evc_event_table_size;
118 int (*pm_evc_allocate_pmc)(enum pmc_event _pe,
119 char *_ctrspec, struct pmc_op_pmcallocate *_pa);
120 };
121
122 #define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0]))
123 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table)
124
125 #undef __PMC_EV
126 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N },
127
128 /*
129 * PMC_CLASSDEP_TABLE(NAME, CLASS)
130 *
131 * Define a table mapping event names and aliases to HWPMC event IDs.
132 */
133 #define PMC_CLASSDEP_TABLE(N, C) \
134 static const struct pmc_event_descr N##_event_table[] = \
135 { \
136 __PMC_EV_##C() \
137 }
138
139 PMC_CLASSDEP_TABLE(iaf, IAF);
140 PMC_CLASSDEP_TABLE(k8, K8);
141 PMC_CLASSDEP_TABLE(ibs, IBS);
142 PMC_CLASSDEP_TABLE(armv7, ARMV7);
143 PMC_CLASSDEP_TABLE(armv8, ARMV8);
144 PMC_CLASSDEP_TABLE(cmn600_pmu, CMN600_PMU);
145 PMC_CLASSDEP_TABLE(dmc620_pmu_cd2, DMC620_PMU_CD2);
146 PMC_CLASSDEP_TABLE(dmc620_pmu_c, DMC620_PMU_C);
147 PMC_CLASSDEP_TABLE(ppc7450, PPC7450);
148 PMC_CLASSDEP_TABLE(ppc970, PPC970);
149 PMC_CLASSDEP_TABLE(e500, E500);
150
151 static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT];
152
153 #undef __PMC_EV_ALIAS
154 #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE },
155
156 /*
157 * TODO: Factor out the __PMC_EV_ARMV7/8 list into a single separate table
158 * rather than duplicating for each core.
159 */
160
161 static const struct pmc_event_descr cortex_a8_event_table[] =
162 {
163 __PMC_EV_ALIAS_ARMV7_CORTEX_A8()
164 __PMC_EV_ARMV7()
165 };
166
167 static const struct pmc_event_descr cortex_a9_event_table[] =
168 {
169 __PMC_EV_ALIAS_ARMV7_CORTEX_A9()
170 __PMC_EV_ARMV7()
171 };
172
173 static const struct pmc_event_descr cortex_a53_event_table[] =
174 {
175 __PMC_EV_ALIAS_ARMV8_CORTEX_A53()
176 __PMC_EV_ARMV8()
177 };
178
179 static const struct pmc_event_descr cortex_a57_event_table[] =
180 {
181 __PMC_EV_ALIAS_ARMV8_CORTEX_A57()
182 __PMC_EV_ARMV8()
183 };
184
185 static const struct pmc_event_descr cortex_a76_event_table[] =
186 {
187 __PMC_EV_ALIAS_ARMV8_CORTEX_A76()
188 __PMC_EV_ARMV8()
189 };
190
191 static const struct pmc_event_descr tsc_event_table[] =
192 {
193 __PMC_EV_ALIAS_TSC()
194 };
195
196 static const struct pmc_event_descr rapl_event_table[] =
197 {
198 __PMC_EV_RAPL()
199 };
200
201 #undef PMC_CLASS_TABLE_DESC
202 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \
203 static const struct pmc_class_descr NAME##_class_table_descr = \
204 { \
205 .pm_evc_name = #CLASS "-", \
206 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \
207 .pm_evc_class = PMC_CLASS_##CLASS , \
208 .pm_evc_event_table = EVENTS##_event_table , \
209 .pm_evc_event_table_size = \
210 PMC_EVENT_TABLE_SIZE(EVENTS), \
211 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \
212 }
213
214 #if defined(__i386__) || defined(__amd64__)
215 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);
216 PMC_CLASS_TABLE_DESC(ibs, IBS, ibs, ibs);
217 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc);
218 PMC_CLASS_TABLE_DESC(rapl, RAPL, rapl, rapl);
219 #endif
220 #if defined(__arm__)
221 PMC_CLASS_TABLE_DESC(cortex_a8, ARMV7, cortex_a8, armv7);
222 PMC_CLASS_TABLE_DESC(cortex_a9, ARMV7, cortex_a9, armv7);
223 #endif
224 #if defined(__aarch64__)
225 PMC_CLASS_TABLE_DESC(cortex_a53, ARMV8, cortex_a53, arm64);
226 PMC_CLASS_TABLE_DESC(cortex_a57, ARMV8, cortex_a57, arm64);
227 PMC_CLASS_TABLE_DESC(cortex_a76, ARMV8, cortex_a76, arm64);
228 PMC_CLASS_TABLE_DESC(cmn600_pmu, CMN600_PMU, cmn600_pmu, cmn600_pmu);
229 PMC_CLASS_TABLE_DESC(dmc620_pmu_cd2, DMC620_PMU_CD2, dmc620_pmu_cd2, dmc620_pmu);
230 PMC_CLASS_TABLE_DESC(dmc620_pmu_c, DMC620_PMU_C, dmc620_pmu_c, dmc620_pmu);
231 #endif
232 #if defined(__powerpc__)
233 PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc);
234 PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc);
235 PMC_CLASS_TABLE_DESC(e500, E500, e500, powerpc);
236 #endif
237
238 static struct pmc_class_descr soft_class_table_descr =
239 {
240 .pm_evc_name = "SOFT-",
241 .pm_evc_name_size = sizeof("SOFT-") - 1,
242 .pm_evc_class = PMC_CLASS_SOFT,
243 .pm_evc_event_table = NULL,
244 .pm_evc_event_table_size = 0,
245 .pm_evc_allocate_pmc = soft_allocate_pmc
246 };
247
248 #undef PMC_CLASS_TABLE_DESC
249
250 static const struct pmc_class_descr **pmc_class_table;
251 #define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass
252
253 /*
254 * Mapping tables, mapping enumeration values to human readable
255 * strings.
256 */
257
258 static const char * pmc_capability_names[] = {
259 #undef __PMC_CAP
260 #define __PMC_CAP(N,V,D) #N ,
261 __PMC_CAPS()
262 };
263
264 struct pmc_class_map {
265 enum pmc_class pm_class;
266 const char *pm_name;
267 };
268
269 static const struct pmc_class_map pmc_class_names[] = {
270 #undef __PMC_CLASS
271 #define __PMC_CLASS(S,V,D) { .pm_class = PMC_CLASS_##S, .pm_name = #S } ,
272 __PMC_CLASSES()
273 };
274
275 struct pmc_cputype_map {
276 enum pmc_cputype pm_cputype;
277 const char *pm_name;
278 };
279
280 static const struct pmc_cputype_map pmc_cputype_names[] = {
281 #undef __PMC_CPU
282 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } ,
283 __PMC_CPUS()
284 };
285
286 static const char * pmc_disposition_names[] = {
287 #undef __PMC_DISP
288 #define __PMC_DISP(D) #D ,
289 __PMC_DISPOSITIONS()
290 };
291
292 static const char * pmc_mode_names[] = {
293 #undef __PMC_MODE
294 #define __PMC_MODE(M,N) #M ,
295 __PMC_MODES()
296 };
297
298 static const char * pmc_state_names[] = {
299 #undef __PMC_STATE
300 #define __PMC_STATE(S) #S ,
301 __PMC_STATES()
302 };
303
304 /*
305 * Filled in by pmc_init().
306 */
307 static int pmc_syscall = -1;
308 static struct pmc_cpuinfo cpu_info;
309 static struct pmc_op_getdyneventinfo soft_event_info;
310
311 /* Event masks for events */
312 struct pmc_masks {
313 const char *pm_name;
314 const uint64_t pm_value;
315 };
316 #define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) }
317 #define NULLMASK { .pm_name = NULL }
318
319 #if defined(__amd64__) || defined(__i386__)
320 static int
pmc_parse_mask(const struct pmc_masks * pmask,char * p,uint64_t * evmask)321 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask)
322 {
323 const struct pmc_masks *pm;
324 char *q, *r;
325 int c;
326
327 if (pmask == NULL) /* no mask keywords */
328 return (-1);
329 q = strchr(p, '='); /* skip '=' */
330 if (*++q == '\0') /* no more data */
331 return (-1);
332 c = 0; /* count of mask keywords seen */
333 while ((r = strsep(&q, "+")) != NULL) {
334 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name);
335 pm++)
336 ;
337 if (pm->pm_name == NULL) /* not found */
338 return (-1);
339 *evmask |= pm->pm_value;
340 c++;
341 }
342 return (c);
343 }
344 #endif
345
346 #define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0)
347 #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0)
348 #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S }
349
350 #if defined(__amd64__) || defined(__i386__)
351 /*
352 * AMD K8 PMCs.
353 *
354 */
355
356 static struct pmc_event_alias k8_aliases[] = {
357 EV_ALIAS("branches", "k8-fr-retired-taken-branches"),
358 EV_ALIAS("branch-mispredicts",
359 "k8-fr-retired-taken-branches-mispredicted"),
360 EV_ALIAS("cycles", "tsc"),
361 EV_ALIAS("dc-misses", "k8-dc-miss"),
362 EV_ALIAS("ic-misses", "k8-ic-miss"),
363 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"),
364 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"),
365 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"),
366 EV_ALIAS(NULL, NULL)
367 };
368
369 #define __K8MASK(N,V) PMCMASK(N,(1 << (V)))
370
371 /*
372 * Parsing tables
373 */
374
375 /* fp dispatched fpu ops */
376 static const struct pmc_masks k8_mask_fdfo[] = {
377 __K8MASK(add-pipe-excluding-junk-ops, 0),
378 __K8MASK(multiply-pipe-excluding-junk-ops, 1),
379 __K8MASK(store-pipe-excluding-junk-ops, 2),
380 __K8MASK(add-pipe-junk-ops, 3),
381 __K8MASK(multiply-pipe-junk-ops, 4),
382 __K8MASK(store-pipe-junk-ops, 5),
383 NULLMASK
384 };
385
386 /* ls segment register loads */
387 static const struct pmc_masks k8_mask_lsrl[] = {
388 __K8MASK(es, 0),
389 __K8MASK(cs, 1),
390 __K8MASK(ss, 2),
391 __K8MASK(ds, 3),
392 __K8MASK(fs, 4),
393 __K8MASK(gs, 5),
394 __K8MASK(hs, 6),
395 NULLMASK
396 };
397
398 /* ls locked operation */
399 static const struct pmc_masks k8_mask_llo[] = {
400 __K8MASK(locked-instructions, 0),
401 __K8MASK(cycles-in-request, 1),
402 __K8MASK(cycles-to-complete, 2),
403 NULLMASK
404 };
405
406 /* dc refill from {l2,system} and dc copyback */
407 static const struct pmc_masks k8_mask_dc[] = {
408 __K8MASK(invalid, 0),
409 __K8MASK(shared, 1),
410 __K8MASK(exclusive, 2),
411 __K8MASK(owner, 3),
412 __K8MASK(modified, 4),
413 NULLMASK
414 };
415
416 /* dc one bit ecc error */
417 static const struct pmc_masks k8_mask_dobee[] = {
418 __K8MASK(scrubber, 0),
419 __K8MASK(piggyback, 1),
420 NULLMASK
421 };
422
423 /* dc dispatched prefetch instructions */
424 static const struct pmc_masks k8_mask_ddpi[] = {
425 __K8MASK(load, 0),
426 __K8MASK(store, 1),
427 __K8MASK(nta, 2),
428 NULLMASK
429 };
430
431 /* dc dcache accesses by locks */
432 static const struct pmc_masks k8_mask_dabl[] = {
433 __K8MASK(accesses, 0),
434 __K8MASK(misses, 1),
435 NULLMASK
436 };
437
438 /* bu internal l2 request */
439 static const struct pmc_masks k8_mask_bilr[] = {
440 __K8MASK(ic-fill, 0),
441 __K8MASK(dc-fill, 1),
442 __K8MASK(tlb-reload, 2),
443 __K8MASK(tag-snoop, 3),
444 __K8MASK(cancelled, 4),
445 NULLMASK
446 };
447
448 /* bu fill request l2 miss */
449 static const struct pmc_masks k8_mask_bfrlm[] = {
450 __K8MASK(ic-fill, 0),
451 __K8MASK(dc-fill, 1),
452 __K8MASK(tlb-reload, 2),
453 NULLMASK
454 };
455
456 /* bu fill into l2 */
457 static const struct pmc_masks k8_mask_bfil[] = {
458 __K8MASK(dirty-l2-victim, 0),
459 __K8MASK(victim-from-l2, 1),
460 NULLMASK
461 };
462
463 /* fr retired fpu instructions */
464 static const struct pmc_masks k8_mask_frfi[] = {
465 __K8MASK(x87, 0),
466 __K8MASK(mmx-3dnow, 1),
467 __K8MASK(packed-sse-sse2, 2),
468 __K8MASK(scalar-sse-sse2, 3),
469 NULLMASK
470 };
471
472 /* fr retired fastpath double op instructions */
473 static const struct pmc_masks k8_mask_frfdoi[] = {
474 __K8MASK(low-op-pos-0, 0),
475 __K8MASK(low-op-pos-1, 1),
476 __K8MASK(low-op-pos-2, 2),
477 NULLMASK
478 };
479
480 /* fr fpu exceptions */
481 static const struct pmc_masks k8_mask_ffe[] = {
482 __K8MASK(x87-reclass-microfaults, 0),
483 __K8MASK(sse-retype-microfaults, 1),
484 __K8MASK(sse-reclass-microfaults, 2),
485 __K8MASK(sse-and-x87-microtraps, 3),
486 NULLMASK
487 };
488
489 /* nb memory controller page access event */
490 static const struct pmc_masks k8_mask_nmcpae[] = {
491 __K8MASK(page-hit, 0),
492 __K8MASK(page-miss, 1),
493 __K8MASK(page-conflict, 2),
494 NULLMASK
495 };
496
497 /* nb memory controller turnaround */
498 static const struct pmc_masks k8_mask_nmct[] = {
499 __K8MASK(dimm-turnaround, 0),
500 __K8MASK(read-to-write-turnaround, 1),
501 __K8MASK(write-to-read-turnaround, 2),
502 NULLMASK
503 };
504
505 /* nb memory controller bypass saturation */
506 static const struct pmc_masks k8_mask_nmcbs[] = {
507 __K8MASK(memory-controller-hi-pri-bypass, 0),
508 __K8MASK(memory-controller-lo-pri-bypass, 1),
509 __K8MASK(dram-controller-interface-bypass, 2),
510 __K8MASK(dram-controller-queue-bypass, 3),
511 NULLMASK
512 };
513
514 /* nb sized commands */
515 static const struct pmc_masks k8_mask_nsc[] = {
516 __K8MASK(nonpostwrszbyte, 0),
517 __K8MASK(nonpostwrszdword, 1),
518 __K8MASK(postwrszbyte, 2),
519 __K8MASK(postwrszdword, 3),
520 __K8MASK(rdszbyte, 4),
521 __K8MASK(rdszdword, 5),
522 __K8MASK(rdmodwr, 6),
523 NULLMASK
524 };
525
526 /* nb probe result */
527 static const struct pmc_masks k8_mask_npr[] = {
528 __K8MASK(probe-miss, 0),
529 __K8MASK(probe-hit, 1),
530 __K8MASK(probe-hit-dirty-no-memory-cancel, 2),
531 __K8MASK(probe-hit-dirty-with-memory-cancel, 3),
532 NULLMASK
533 };
534
535 /* nb hypertransport bus bandwidth */
536 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */
537 __K8MASK(command, 0),
538 __K8MASK(data, 1),
539 __K8MASK(buffer-release, 2),
540 __K8MASK(nop, 3),
541 NULLMASK
542 };
543
544 #undef __K8MASK
545
546 #define K8_KW_COUNT "count"
547 #define K8_KW_EDGE "edge"
548 #define K8_KW_INV "inv"
549 #define K8_KW_MASK "mask"
550 #define K8_KW_OS "os"
551 #define K8_KW_USR "usr"
552
553 static int
k8_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)554 k8_allocate_pmc(enum pmc_event pe, char *ctrspec,
555 struct pmc_op_pmcallocate *pmc_config)
556 {
557 char *e, *p, *q;
558 int n;
559 uint32_t count;
560 uint64_t evmask;
561 const struct pmc_masks *pm, *pmask;
562
563 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
564 pmc_config->pm_md.pm_amd.pm_amd_config = 0;
565
566 pmask = NULL;
567 evmask = 0;
568
569 #define __K8SETMASK(M) pmask = k8_mask_##M
570
571 /* setup parsing tables */
572 switch (pe) {
573 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
574 __K8SETMASK(fdfo);
575 break;
576 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD:
577 __K8SETMASK(lsrl);
578 break;
579 case PMC_EV_K8_LS_LOCKED_OPERATION:
580 __K8SETMASK(llo);
581 break;
582 case PMC_EV_K8_DC_REFILL_FROM_L2:
583 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM:
584 case PMC_EV_K8_DC_COPYBACK:
585 __K8SETMASK(dc);
586 break;
587 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR:
588 __K8SETMASK(dobee);
589 break;
590 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS:
591 __K8SETMASK(ddpi);
592 break;
593 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
594 __K8SETMASK(dabl);
595 break;
596 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST:
597 __K8SETMASK(bilr);
598 break;
599 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS:
600 __K8SETMASK(bfrlm);
601 break;
602 case PMC_EV_K8_BU_FILL_INTO_L2:
603 __K8SETMASK(bfil);
604 break;
605 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
606 __K8SETMASK(frfi);
607 break;
608 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
609 __K8SETMASK(frfdoi);
610 break;
611 case PMC_EV_K8_FR_FPU_EXCEPTIONS:
612 __K8SETMASK(ffe);
613 break;
614 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT:
615 __K8SETMASK(nmcpae);
616 break;
617 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND:
618 __K8SETMASK(nmct);
619 break;
620 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION:
621 __K8SETMASK(nmcbs);
622 break;
623 case PMC_EV_K8_NB_SIZED_COMMANDS:
624 __K8SETMASK(nsc);
625 break;
626 case PMC_EV_K8_NB_PROBE_RESULT:
627 __K8SETMASK(npr);
628 break;
629 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH:
630 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH:
631 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH:
632 __K8SETMASK(nhbb);
633 break;
634
635 default:
636 break; /* no options defined */
637 }
638
639 while ((p = strsep(&ctrspec, ",")) != NULL) {
640 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) {
641 q = strchr(p, '=');
642 if (*++q == '\0') /* skip '=' */
643 return (-1);
644
645 count = strtol(q, &e, 0);
646 if (e == q || *e != '\0')
647 return (-1);
648
649 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
650 pmc_config->pm_md.pm_amd.pm_amd_config |=
651 AMD_PMC_TO_COUNTER(count);
652
653 } else if (KWMATCH(p, K8_KW_EDGE)) {
654 pmc_config->pm_caps |= PMC_CAP_EDGE;
655 } else if (KWMATCH(p, K8_KW_INV)) {
656 pmc_config->pm_caps |= PMC_CAP_INVERT;
657 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) {
658 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
659 return (-1);
660 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
661 } else if (KWMATCH(p, K8_KW_OS)) {
662 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
663 } else if (KWMATCH(p, K8_KW_USR)) {
664 pmc_config->pm_caps |= PMC_CAP_USER;
665 } else
666 return (-1);
667 }
668
669 /* other post processing */
670 switch (pe) {
671 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
672 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED:
673 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS:
674 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
675 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
676 case PMC_EV_K8_FR_FPU_EXCEPTIONS:
677 /* XXX only available in rev B and later */
678 break;
679 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
680 /* XXX only available in rev C and later */
681 break;
682 case PMC_EV_K8_LS_LOCKED_OPERATION:
683 /* XXX CPU Rev A,B evmask is to be zero */
684 if (evmask & (evmask - 1)) /* > 1 bit set */
685 return (-1);
686 if (evmask == 0) {
687 evmask = 0x01; /* Rev C and later: #instrs */
688 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
689 }
690 break;
691 default:
692 if (evmask == 0 && pmask != NULL) {
693 for (pm = pmask; pm->pm_name; pm++)
694 evmask |= pm->pm_value;
695 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
696 }
697 }
698
699 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
700 pmc_config->pm_md.pm_amd.pm_amd_config =
701 AMD_PMC_TO_UNITMASK(evmask);
702
703 return (0);
704 }
705
706 static int
ibs_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)707 ibs_allocate_pmc(enum pmc_event pe, char *ctrspec,
708 struct pmc_op_pmcallocate *pmc_config)
709 {
710 char *e, *p, *q;
711 uint64_t ctl, ctl2, ldlat, fetchlat;
712 u_int ibs_features;
713 u_int regs[4];
714
715 pmc_config->pm_caps |=
716 (PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_PRECISE);
717 pmc_config->pm_md.pm_ibs.ibs_ctl = 0;
718 pmc_config->pm_md.pm_ibs.ibs_ctl2 = 0;
719
720 /* setup parsing tables */
721 switch (pe) {
722 case PMC_EV_IBS_FETCH:
723 pmc_config->pm_md.pm_ibs.ibs_type = IBS_PMC_FETCH;
724 break;
725 case PMC_EV_IBS_OP:
726 pmc_config->pm_md.pm_ibs.ibs_type = IBS_PMC_OP;
727 break;
728 default:
729 return (-1);
730 }
731
732 /* IBS only supports sampling mode */
733 if (!PMC_IS_SAMPLING_MODE(pmc_config->pm_mode)) {
734 return (-1);
735 }
736
737 /* Read the ibs feature flags */
738 ibs_features = 0;
739 do_cpuid(0x80000000, regs);
740 if (regs[0] >= CPUID_IBSID) {
741 do_cpuid(CPUID_IBSID, regs);
742 ibs_features = regs[0];
743 }
744
745 /* parse parameters */
746 ctl = 0;
747 ctl2 = 0;
748 if (pe == PMC_EV_IBS_FETCH) {
749 while ((p = strsep(&ctrspec, ",")) != NULL) {
750 if (KWMATCH(p, "l3miss")) {
751 if ((ibs_features & CPUID_IBSID_ZEN4IBSEXTENSIONS) == 0)
752 return (-1);
753
754 ctl |= IBS_FETCH_CTL_L3MISSONLY;
755 } else if (KWMATCH(p, "randomize")) {
756 ctl |= IBS_FETCH_CTL_RANDOMIZE;
757 } else if (KWPREFIXMATCH(p, "fetchlat=")) {
758 if ((ibs_features & CPUID_IBSID_FETCHLATFILTERING) == 0)
759 return (-1);
760
761 q = strchr(p, '=');
762 if (*++q == '\0')
763 return (-1);
764
765 fetchlat = strtoull(q, &e, 0);
766 if (e == q || *e != '\0')
767 return (-1);
768
769 if (fetchlat < IBS_FETCH_CTL2_LAT_MIN ||
770 fetchlat > IBS_FETCH_CTL2_LAT_MAX)
771 return (-1);
772 if ((fetchlat % IBS_FETCH_CTL2_LAT_STEP) != 0)
773 return (-1);
774
775 /* clear prior threshold */
776 ctl2 &= ~IBS_FETCH_CTL2_LATFILTERMASK;
777 ctl2 |= IBS_FETCH_CTL2_LAT_TO_CTL(fetchlat);
778 } else if (KWMATCH(p, "usr")) {
779 if ((ibs_features & CPUID_IBSID_ADDRBIT63FILTERING) == 0)
780 return (-1);
781
782 pmc_config->pm_caps |= PMC_CAP_USER;
783 } else if (KWMATCH(p, "os")) {
784 if ((ibs_features & CPUID_IBSID_ADDRBIT63FILTERING) == 0)
785 return (-1);
786
787 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
788 } else {
789 return (-1);
790 }
791 }
792
793 if (pmc_config->pm_count < IBS_FETCH_MIN_RATE ||
794 pmc_config->pm_count > IBS_FETCH_MAX_RATE)
795 return (-1);
796
797 ctl |= IBS_FETCH_INTERVAL_TO_CTL(pmc_config->pm_count);
798 } else {
799 while ((p = strsep(&ctrspec, ",")) != NULL) {
800 if (KWMATCH(p, "l3miss")) {
801 ctl |= IBS_OP_CTL_L3MISSONLY;
802 } else if (KWPREFIXMATCH(p, "ldlat=")) {
803 if ((ibs_features & CPUID_IBSID_IBSLOADLATENCYFILT) == 0)
804 return (-1);
805
806 q = strchr(p, '=');
807 if (*++q == '\0') /* skip '=' */
808 return (-1);
809
810 ldlat = strtoull(q, &e, 0);
811 if (e == q || *e != '\0')
812 return (-1);
813
814 /*
815 * IBS load latency filtering requires the
816 * latency to be a multiple of 128 and between
817 * 128 and 2048. The latency is stored in the
818 * IbsOpLatThrsh field, which only contains
819 * four bits so the processor computes
820 * (IbsOpLatThrsh+1)*128 as the value.
821 *
822 * AMD PPR Vol 1 for AMD Family 1Ah Model 02h
823 * C1 (57238) 2026-03-06 Revision 0.49.
824 */
825 if (ldlat < 128 || ldlat > 2048)
826 return (-1);
827
828 /* clear prior ldlat threshold */
829 ctl &= ~IBS_OP_CTL_LDLATTRSHMASK;
830 ctl |= IBS_OP_CTL_LDLAT_TO_CTL(ldlat);
831 ctl |= IBS_OP_CTL_L3MISSONLY | IBS_OP_CTL_LATFLTEN;
832 } else if (KWMATCH(p, "opcount")) {
833 if ((ibs_features & CPUID_IBSID_OPCNT) == 0)
834 return (-1);
835
836 ctl |= IBS_OP_CTL_COUNTERCONTROL;
837 } else if (KWMATCH(p, "usr")) {
838 if ((ibs_features & CPUID_IBSID_ADDRBIT63FILTERING) == 0)
839 return (-1);
840
841 pmc_config->pm_caps |= PMC_CAP_USER;
842 } else if (KWMATCH(p, "os")) {
843 if ((ibs_features & CPUID_IBSID_ADDRBIT63FILTERING) == 0)
844 return (-1);
845
846 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
847 } else if (KWMATCH(p, "streamstore")) {
848 if ((ibs_features & CPUID_IBSID_STRMSTANDRMTSOCKET) == 0)
849 return (-1);
850
851 ctl2 |= IBS_OP_CTL2_STRMSTFILTER;
852 } else {
853 return (-1);
854 }
855 }
856
857 if (pmc_config->pm_count < IBS_OP_MIN_RATE ||
858 pmc_config->pm_count > IBS_OP_MAX_RATE)
859 return (-1);
860
861 if (((ibs_features & CPUID_IBSID_OPCNTEXT) == 0) &&
862 (pmc_config->pm_count > IBS_OP_MAX_RATE_PREEXT))
863 return (-1);
864
865 ctl |= IBS_OP_INTERVAL_TO_CTL(pmc_config->pm_count);
866 }
867
868 pmc_config->pm_md.pm_ibs.ibs_ctl |= ctl;
869 pmc_config->pm_md.pm_ibs.ibs_ctl2 |= ctl2;
870
871 return (0);
872 }
873
874 static int
tsc_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)875 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec,
876 struct pmc_op_pmcallocate *pmc_config)
877 {
878 if (pe != PMC_EV_TSC_TSC)
879 return (-1);
880
881 /* TSC events must be unqualified. */
882 if (ctrspec && *ctrspec != '\0')
883 return (-1);
884
885 pmc_config->pm_md.pm_amd.pm_amd_config = 0;
886 pmc_config->pm_caps |= PMC_CAP_READ;
887
888 return (0);
889 }
890
891 static int
rapl_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)892 rapl_allocate_pmc(enum pmc_event pe, char *ctrspec,
893 struct pmc_op_pmcallocate *pmc_config)
894 {
895 if (pe < PMC_EV_RAPL_FIRST || pe > PMC_EV_RAPL_LAST)
896 return (-1);
897
898 /* RAPL events must be unqualified. */
899 if (ctrspec != NULL && *ctrspec != '\0')
900 return (-1);
901
902 pmc_config->pm_caps |= PMC_CAP_READ;
903
904 return (0);
905 }
906 #endif
907
908 static struct pmc_event_alias generic_aliases[] = {
909 EV_ALIAS("instructions", "SOFT-CLOCK.HARD"),
910 EV_ALIAS(NULL, NULL)
911 };
912
913 static int
soft_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)914 soft_allocate_pmc(enum pmc_event pe, char *ctrspec,
915 struct pmc_op_pmcallocate *pmc_config)
916 {
917 (void)ctrspec;
918 (void)pmc_config;
919
920 if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST)
921 return (-1);
922
923 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
924 return (0);
925 }
926
927 #if defined(__arm__)
928 static struct pmc_event_alias cortex_a8_aliases[] = {
929 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"),
930 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"),
931 EV_ALIAS("instructions", "INSTR_EXECUTED"),
932 EV_ALIAS(NULL, NULL)
933 };
934
935 static struct pmc_event_alias cortex_a9_aliases[] = {
936 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"),
937 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"),
938 EV_ALIAS("instructions", "INSTR_EXECUTED"),
939 EV_ALIAS(NULL, NULL)
940 };
941
942 static int
armv7_allocate_pmc(enum pmc_event pe,char * ctrspec __unused,struct pmc_op_pmcallocate * pmc_config __unused)943 armv7_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
944 struct pmc_op_pmcallocate *pmc_config __unused)
945 {
946 switch (pe) {
947 default:
948 break;
949 }
950
951 return (0);
952 }
953 #endif
954
955 #if defined(__aarch64__)
956 static struct pmc_event_alias cortex_a53_aliases[] = {
957 EV_ALIAS(NULL, NULL)
958 };
959 static struct pmc_event_alias cortex_a57_aliases[] = {
960 EV_ALIAS(NULL, NULL)
961 };
962 static struct pmc_event_alias cortex_a76_aliases[] = {
963 EV_ALIAS(NULL, NULL)
964 };
965
966 static int
arm64_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)967 arm64_allocate_pmc(enum pmc_event pe, char *ctrspec,
968 struct pmc_op_pmcallocate *pmc_config)
969 {
970 char *p;
971
972 while ((p = strsep(&ctrspec, ",")) != NULL) {
973 if (KWMATCH(p, "os"))
974 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
975 else if (KWMATCH(p, "usr"))
976 pmc_config->pm_caps |= PMC_CAP_USER;
977 else
978 return (-1);
979 }
980
981 return (0);
982 }
983
984 static int
cmn600_pmu_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)985 cmn600_pmu_allocate_pmc(enum pmc_event pe, char *ctrspec,
986 struct pmc_op_pmcallocate *pmc_config)
987 {
988 uint32_t nodeid, occupancy, xpport, xpchannel;
989 char *e, *p, *q;
990 unsigned int i;
991 char *xpport_names[] = { "East", "West", "North", "South", "devport0",
992 "devport1" };
993 char *xpchannel_names[] = { "REQ", "RSP", "SNP", "DAT" };
994
995 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
996 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
997 pmc_config->pm_md.pm_cmn600.pma_cmn600_config = 0;
998 /*
999 * CMN600 extra fields:
1000 * * nodeid - node coordinates x[2-3],y[2-3],p[1],s[2]
1001 * width of x and y fields depend on matrix size.
1002 * * occupancy - numeric value to select desired filter.
1003 * * xpport - East, West, North, South, devport0, devport1 (or 0, 1, ..., 5)
1004 * * xpchannel - REQ, RSP, SNP, DAT (or 0, 1, 2, 3)
1005 */
1006
1007 while ((p = strsep(&ctrspec, ",")) != NULL) {
1008 if (KWPREFIXMATCH(p, "nodeid=")) {
1009 q = strchr(p, '=');
1010 if (*++q == '\0') /* skip '=' */
1011 return (-1);
1012
1013 nodeid = strtol(q, &e, 0);
1014 if (e == q || *e != '\0')
1015 return (-1);
1016
1017 pmc_config->pm_md.pm_cmn600.pma_cmn600_nodeid |= nodeid;
1018
1019 } else if (KWPREFIXMATCH(p, "occupancy=")) {
1020 q = strchr(p, '=');
1021 if (*++q == '\0') /* skip '=' */
1022 return (-1);
1023
1024 occupancy = strtol(q, &e, 0);
1025 if (e == q || *e != '\0')
1026 return (-1);
1027
1028 pmc_config->pm_md.pm_cmn600.pma_cmn600_occupancy = occupancy;
1029 } else if (KWPREFIXMATCH(p, "xpport=")) {
1030 q = strchr(p, '=');
1031 if (*++q == '\0') /* skip '=' */
1032 return (-1);
1033
1034 xpport = strtol(q, &e, 0);
1035 if (e == q || *e != '\0') {
1036 for (i = 0; i < nitems(xpport_names); i++) {
1037 if (strcasecmp(xpport_names[i], q) == 0) {
1038 xpport = i;
1039 break;
1040 }
1041 }
1042 if (i == nitems(xpport_names))
1043 return (-1);
1044 }
1045
1046 pmc_config->pm_md.pm_cmn600.pma_cmn600_config |= xpport << 2;
1047 } else if (KWPREFIXMATCH(p, "xpchannel=")) {
1048 q = strchr(p, '=');
1049 if (*++q == '\0') /* skip '=' */
1050 return (-1);
1051
1052 xpchannel = strtol(q, &e, 0);
1053 if (e == q || *e != '\0') {
1054 for (i = 0; i < nitems(xpchannel_names); i++) {
1055 if (strcasecmp(xpchannel_names[i], q) == 0) {
1056 xpchannel = i;
1057 break;
1058 }
1059 }
1060 if (i == nitems(xpchannel_names))
1061 return (-1);
1062 }
1063
1064 pmc_config->pm_md.pm_cmn600.pma_cmn600_config |= xpchannel << 5;
1065 } else
1066 return (-1);
1067 }
1068
1069 return (0);
1070 }
1071
1072 static int
dmc620_pmu_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)1073 dmc620_pmu_allocate_pmc(enum pmc_event pe, char *ctrspec,
1074 struct pmc_op_pmcallocate *pmc_config)
1075 {
1076 char *e, *p, *q;
1077 uint64_t match, mask;
1078 uint32_t count;
1079
1080 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1081 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1082 pmc_config->pm_md.pm_dmc620.pm_dmc620_config = 0;
1083
1084 while ((p = strsep(&ctrspec, ",")) != NULL) {
1085 if (KWPREFIXMATCH(p, "count=")) {
1086 q = strchr(p, '=');
1087 if (*++q == '\0') /* skip '=' */
1088 return (-1);
1089
1090 count = strtol(q, &e, 0);
1091 if (e == q || *e != '\0')
1092 return (-1);
1093
1094 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1095 pmc_config->pm_md.pm_dmc620.pm_dmc620_config |= count;
1096
1097 } else if (KWMATCH(p, "inv")) {
1098 pmc_config->pm_caps |= PMC_CAP_INVERT;
1099 } else if (KWPREFIXMATCH(p, "match=")) {
1100 match = strtol(q, &e, 0);
1101 if (e == q || *e != '\0')
1102 return (-1);
1103
1104 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1105 pmc_config->pm_md.pm_dmc620.pm_dmc620_match = match;
1106 } else if (KWPREFIXMATCH(p, "mask=")) {
1107 q = strchr(p, '=');
1108 if (*++q == '\0') /* skip '=' */
1109 return (-1);
1110
1111 mask = strtol(q, &e, 0);
1112 if (e == q || *e != '\0')
1113 return (-1);
1114
1115 pmc_config->pm_md.pm_dmc620.pm_dmc620_mask = mask;
1116 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1117 } else
1118 return (-1);
1119 }
1120
1121 return (0);
1122 }
1123 #endif
1124
1125 #if defined(__powerpc__)
1126
1127 static struct pmc_event_alias ppc7450_aliases[] = {
1128 EV_ALIAS("instructions", "INSTR_COMPLETED"),
1129 EV_ALIAS("branches", "BRANCHES_COMPLETED"),
1130 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"),
1131 EV_ALIAS(NULL, NULL)
1132 };
1133
1134 static struct pmc_event_alias ppc970_aliases[] = {
1135 EV_ALIAS("instructions", "INSTR_COMPLETED"),
1136 EV_ALIAS("cycles", "CYCLES"),
1137 EV_ALIAS(NULL, NULL)
1138 };
1139
1140 static struct pmc_event_alias e500_aliases[] = {
1141 EV_ALIAS("instructions", "INSTR_COMPLETED"),
1142 EV_ALIAS("cycles", "CYCLES"),
1143 EV_ALIAS(NULL, NULL)
1144 };
1145
1146 #define POWERPC_KW_OS "os"
1147 #define POWERPC_KW_USR "usr"
1148 #define POWERPC_KW_ANYTHREAD "anythread"
1149
1150 static int
powerpc_allocate_pmc(enum pmc_event pe,char * ctrspec __unused,struct pmc_op_pmcallocate * pmc_config __unused)1151 powerpc_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
1152 struct pmc_op_pmcallocate *pmc_config __unused)
1153 {
1154 char *p;
1155
1156 (void) pe;
1157
1158 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1159
1160 while ((p = strsep(&ctrspec, ",")) != NULL) {
1161 if (KWMATCH(p, POWERPC_KW_OS))
1162 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1163 else if (KWMATCH(p, POWERPC_KW_USR))
1164 pmc_config->pm_caps |= PMC_CAP_USER;
1165 else if (KWMATCH(p, POWERPC_KW_ANYTHREAD))
1166 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
1167 else
1168 return (-1);
1169 }
1170
1171 return (0);
1172 }
1173
1174 #endif /* __powerpc__ */
1175
1176
1177 /*
1178 * Match an event name `name' with its canonical form.
1179 *
1180 * Matches are case insensitive and spaces, periods, underscores and
1181 * hyphen characters are considered to match each other.
1182 *
1183 * Returns 1 for a match, 0 otherwise.
1184 */
1185
1186 static int
pmc_match_event_name(const char * name,const char * canonicalname)1187 pmc_match_event_name(const char *name, const char *canonicalname)
1188 {
1189 int cc, nc;
1190 const unsigned char *c, *n;
1191
1192 c = (const unsigned char *) canonicalname;
1193 n = (const unsigned char *) name;
1194
1195 for (; (nc = *n) && (cc = *c); n++, c++) {
1196
1197 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') &&
1198 (cc == ' ' || cc == '_' || cc == '-' || cc == '.'))
1199 continue;
1200
1201 if (toupper(nc) == toupper(cc))
1202 continue;
1203
1204
1205 return (0);
1206 }
1207
1208 if (*n == '\0' && *c == '\0')
1209 return (1);
1210
1211 return (0);
1212 }
1213
1214 /*
1215 * Match an event name against all the event named supported by a
1216 * PMC class.
1217 *
1218 * Returns an event descriptor pointer on match or NULL otherwise.
1219 */
1220 static const struct pmc_event_descr *
pmc_match_event_class(const char * name,const struct pmc_class_descr * pcd)1221 pmc_match_event_class(const char *name,
1222 const struct pmc_class_descr *pcd)
1223 {
1224 size_t n;
1225 const struct pmc_event_descr *ev;
1226
1227 ev = pcd->pm_evc_event_table;
1228 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++)
1229 if (pmc_match_event_name(name, ev->pm_ev_name))
1230 return (ev);
1231
1232 return (NULL);
1233 }
1234
1235 /*
1236 * API entry points
1237 */
1238
1239 int
pmc_allocate(const char * ctrspec,enum pmc_mode mode,uint32_t flags,int cpu,pmc_id_t * pmcid,uint64_t count)1240 pmc_allocate(const char *ctrspec, enum pmc_mode mode,
1241 uint32_t flags, int cpu, pmc_id_t *pmcid,
1242 uint64_t count)
1243 {
1244 size_t n;
1245 int retval;
1246 char *r, *spec_copy;
1247 const char *ctrname;
1248 const struct pmc_event_descr *ev;
1249 const struct pmc_event_alias *alias;
1250 struct pmc_op_pmcallocate pmc_config;
1251 const struct pmc_class_descr *pcd;
1252
1253 spec_copy = NULL;
1254 retval = -1;
1255
1256 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS &&
1257 mode != PMC_MODE_SC && mode != PMC_MODE_TC) {
1258 errno = EINVAL;
1259 goto out;
1260 }
1261 bzero(&pmc_config, sizeof(pmc_config));
1262 pmc_config.pm_cpu = cpu;
1263 pmc_config.pm_mode = mode;
1264 pmc_config.pm_flags = flags;
1265 pmc_config.pm_count = count;
1266 if (PMC_IS_SAMPLING_MODE(mode))
1267 pmc_config.pm_caps |= PMC_CAP_INTERRUPT;
1268
1269 /*
1270 * Try to pull the raw event ID directly from the pmu-events table. If
1271 * this is unsupported on the platform, or the event is not found,
1272 * continue with searching the regular event tables.
1273 */
1274 r = spec_copy = strdup(ctrspec);
1275 ctrname = strsep(&r, ",");
1276 if (pmc_pmu_enabled()) {
1277 errno = pmc_pmu_pmcallocate(ctrname, &pmc_config);
1278 if (errno == 0)
1279 goto found;
1280 if (errno == EOPNOTSUPP)
1281 goto out;
1282 }
1283 free(spec_copy);
1284 spec_copy = NULL;
1285
1286 /* replace an event alias with the canonical event specifier */
1287 if (pmc_mdep_event_aliases)
1288 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++)
1289 if (!strcasecmp(ctrspec, alias->pm_alias)) {
1290 spec_copy = strdup(alias->pm_spec);
1291 break;
1292 }
1293
1294 if (spec_copy == NULL)
1295 spec_copy = strdup(ctrspec);
1296
1297 r = spec_copy;
1298 ctrname = strsep(&r, ",");
1299
1300 /*
1301 * If a explicit class prefix was given by the user, restrict the
1302 * search for the event to the specified PMC class.
1303 */
1304 ev = NULL;
1305 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) {
1306 pcd = pmc_class_table[n];
1307 if (pcd != NULL && strncasecmp(ctrname, pcd->pm_evc_name,
1308 pcd->pm_evc_name_size) == 0) {
1309 if ((ev = pmc_match_event_class(ctrname +
1310 pcd->pm_evc_name_size, pcd)) == NULL) {
1311 errno = EINVAL;
1312 goto out;
1313 }
1314 break;
1315 }
1316 }
1317
1318 /*
1319 * Otherwise, search for this event in all compatible PMC
1320 * classes.
1321 */
1322 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) {
1323 pcd = pmc_class_table[n];
1324 if (pcd != NULL)
1325 ev = pmc_match_event_class(ctrname, pcd);
1326 }
1327
1328 if (ev == NULL) {
1329 errno = EINVAL;
1330 goto out;
1331 }
1332
1333 pmc_config.pm_ev = ev->pm_ev_code;
1334 pmc_config.pm_class = pcd->pm_evc_class;
1335
1336 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) {
1337 errno = EINVAL;
1338 goto out;
1339 }
1340
1341 found:
1342 if (PMC_CALL(PMC_OP_PMCALLOCATE, &pmc_config) == 0) {
1343 *pmcid = pmc_config.pm_pmcid;
1344 retval = 0;
1345 }
1346 out:
1347 if (spec_copy)
1348 free(spec_copy);
1349
1350 return (retval);
1351 }
1352
1353 int
pmc_attach(pmc_id_t pmc,pid_t pid)1354 pmc_attach(pmc_id_t pmc, pid_t pid)
1355 {
1356 struct pmc_op_pmcattach pmc_attach_args;
1357
1358 pmc_attach_args.pm_pmc = pmc;
1359 pmc_attach_args.pm_pid = pid;
1360
1361 return (PMC_CALL(PMC_OP_PMCATTACH, &pmc_attach_args));
1362 }
1363
1364 int
pmc_capabilities(pmc_id_t pmcid,uint32_t * caps)1365 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps)
1366 {
1367 struct pmc_op_caps args;
1368 int status;
1369
1370 args.pm_pmcid = pmcid;
1371 args.pm_caps = 0;
1372
1373 status = PMC_CALL(PMC_OP_GETCAPS, &args);
1374 *caps = args.pm_caps;
1375
1376 return (status);
1377 }
1378
1379 int
pmc_configure_logfile(int fd)1380 pmc_configure_logfile(int fd)
1381 {
1382 struct pmc_op_configurelog cla;
1383
1384 cla.pm_flags = 0;
1385 cla.pm_logfd = fd;
1386 if (PMC_CALL(PMC_OP_CONFIGURELOG, &cla) < 0)
1387 return (-1);
1388 return (0);
1389 }
1390
1391 int
pmc_cpuinfo(const struct pmc_cpuinfo ** pci)1392 pmc_cpuinfo(const struct pmc_cpuinfo **pci)
1393 {
1394 if (pmc_syscall == -1) {
1395 errno = ENXIO;
1396 return (-1);
1397 }
1398
1399 *pci = &cpu_info;
1400 return (0);
1401 }
1402
1403 int
pmc_detach(pmc_id_t pmc,pid_t pid)1404 pmc_detach(pmc_id_t pmc, pid_t pid)
1405 {
1406 struct pmc_op_pmcattach pmc_detach_args;
1407
1408 pmc_detach_args.pm_pmc = pmc;
1409 pmc_detach_args.pm_pid = pid;
1410 return (PMC_CALL(PMC_OP_PMCDETACH, &pmc_detach_args));
1411 }
1412
1413 int
pmc_disable(int cpu,int pmc)1414 pmc_disable(int cpu, int pmc)
1415 {
1416 struct pmc_op_pmcadmin ssa;
1417
1418 ssa.pm_cpu = cpu;
1419 ssa.pm_pmc = pmc;
1420 ssa.pm_state = PMC_STATE_DISABLED;
1421 return (PMC_CALL(PMC_OP_PMCADMIN, &ssa));
1422 }
1423
1424 int
pmc_enable(int cpu,int pmc)1425 pmc_enable(int cpu, int pmc)
1426 {
1427 struct pmc_op_pmcadmin ssa;
1428
1429 ssa.pm_cpu = cpu;
1430 ssa.pm_pmc = pmc;
1431 ssa.pm_state = PMC_STATE_FREE;
1432 return (PMC_CALL(PMC_OP_PMCADMIN, &ssa));
1433 }
1434
1435 /*
1436 * Return a list of events known to a given PMC class. 'cl' is the
1437 * PMC class identifier, 'eventnames' is the returned list of 'const
1438 * char *' pointers pointing to the names of the events. 'nevents' is
1439 * the number of event name pointers returned.
1440 *
1441 * The space for 'eventnames' is allocated using malloc(3). The caller
1442 * is responsible for freeing this space when done.
1443 */
1444 int
pmc_event_names_of_class(enum pmc_class cl,const char *** eventnames,int * nevents)1445 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
1446 int *nevents)
1447 {
1448 int count;
1449 const char **names;
1450 const struct pmc_event_descr *ev;
1451
1452 switch (cl)
1453 {
1454 case PMC_CLASS_IAF:
1455 ev = iaf_event_table;
1456 count = PMC_EVENT_TABLE_SIZE(iaf);
1457 break;
1458 case PMC_CLASS_TSC:
1459 ev = tsc_event_table;
1460 count = PMC_EVENT_TABLE_SIZE(tsc);
1461 break;
1462 case PMC_CLASS_RAPL:
1463 ev = rapl_event_table;
1464 count = PMC_EVENT_TABLE_SIZE(rapl);
1465 break;
1466 case PMC_CLASS_K8:
1467 ev = k8_event_table;
1468 count = PMC_EVENT_TABLE_SIZE(k8);
1469 break;
1470 case PMC_CLASS_IBS:
1471 ev = ibs_event_table;
1472 count = PMC_EVENT_TABLE_SIZE(ibs);
1473 break;
1474 case PMC_CLASS_ARMV7:
1475 switch (cpu_info.pm_cputype) {
1476 default:
1477 case PMC_CPU_ARMV7_CORTEX_A8:
1478 ev = cortex_a8_event_table;
1479 count = PMC_EVENT_TABLE_SIZE(cortex_a8);
1480 break;
1481 case PMC_CPU_ARMV7_CORTEX_A9:
1482 ev = cortex_a9_event_table;
1483 count = PMC_EVENT_TABLE_SIZE(cortex_a9);
1484 break;
1485 }
1486 break;
1487 case PMC_CLASS_ARMV8:
1488 switch (cpu_info.pm_cputype) {
1489 default:
1490 case PMC_CPU_ARMV8_CORTEX_A53:
1491 ev = cortex_a53_event_table;
1492 count = PMC_EVENT_TABLE_SIZE(cortex_a53);
1493 break;
1494 case PMC_CPU_ARMV8_CORTEX_A57:
1495 ev = cortex_a57_event_table;
1496 count = PMC_EVENT_TABLE_SIZE(cortex_a57);
1497 break;
1498 case PMC_CPU_ARMV8_CORTEX_A76:
1499 ev = cortex_a76_event_table;
1500 count = PMC_EVENT_TABLE_SIZE(cortex_a76);
1501 break;
1502 }
1503 break;
1504 case PMC_CLASS_CMN600_PMU:
1505 ev = cmn600_pmu_event_table;
1506 count = PMC_EVENT_TABLE_SIZE(cmn600_pmu);
1507 break;
1508 case PMC_CLASS_DMC620_PMU_CD2:
1509 ev = dmc620_pmu_cd2_event_table;
1510 count = PMC_EVENT_TABLE_SIZE(dmc620_pmu_cd2);
1511 break;
1512 case PMC_CLASS_DMC620_PMU_C:
1513 ev = dmc620_pmu_c_event_table;
1514 count = PMC_EVENT_TABLE_SIZE(dmc620_pmu_c);
1515 break;
1516 case PMC_CLASS_PPC7450:
1517 ev = ppc7450_event_table;
1518 count = PMC_EVENT_TABLE_SIZE(ppc7450);
1519 break;
1520 case PMC_CLASS_PPC970:
1521 ev = ppc970_event_table;
1522 count = PMC_EVENT_TABLE_SIZE(ppc970);
1523 break;
1524 case PMC_CLASS_E500:
1525 ev = e500_event_table;
1526 count = PMC_EVENT_TABLE_SIZE(e500);
1527 break;
1528 case PMC_CLASS_SOFT:
1529 ev = soft_event_table;
1530 count = soft_event_info.pm_nevent;
1531 break;
1532 default:
1533 errno = EINVAL;
1534 return (-1);
1535 }
1536
1537 if ((names = malloc(count * sizeof(const char *))) == NULL)
1538 return (-1);
1539
1540 *eventnames = names;
1541 *nevents = count;
1542
1543 for (;count--; ev++, names++)
1544 *names = ev->pm_ev_name;
1545
1546 return (0);
1547 }
1548
1549 int
pmc_flush_logfile(void)1550 pmc_flush_logfile(void)
1551 {
1552 return (PMC_CALL(PMC_OP_FLUSHLOG, 0));
1553 }
1554
1555 int
pmc_close_logfile(void)1556 pmc_close_logfile(void)
1557 {
1558 return (PMC_CALL(PMC_OP_CLOSELOG, 0));
1559 }
1560
1561 int
pmc_get_driver_stats(struct pmc_driverstats * ds)1562 pmc_get_driver_stats(struct pmc_driverstats *ds)
1563 {
1564 struct pmc_op_getdriverstats gms;
1565
1566 if (PMC_CALL(PMC_OP_GETDRIVERSTATS, &gms) < 0)
1567 return (-1);
1568
1569 /* copy out fields in the current userland<->library interface */
1570 ds->pm_intr_ignored = gms.pm_intr_ignored;
1571 ds->pm_intr_processed = gms.pm_intr_processed;
1572 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull;
1573 ds->pm_syscalls = gms.pm_syscalls;
1574 ds->pm_syscall_errors = gms.pm_syscall_errors;
1575 ds->pm_buffer_requests = gms.pm_buffer_requests;
1576 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed;
1577 ds->pm_log_sweeps = gms.pm_log_sweeps;
1578 return (0);
1579 }
1580
1581 int
pmc_get_msr(pmc_id_t pmc,uint32_t * msr)1582 pmc_get_msr(pmc_id_t pmc, uint32_t *msr)
1583 {
1584 struct pmc_op_getmsr gm;
1585
1586 gm.pm_pmcid = pmc;
1587 if (PMC_CALL(PMC_OP_PMCGETMSR, &gm) < 0)
1588 return (-1);
1589 *msr = gm.pm_msr;
1590 return (0);
1591 }
1592
1593 int
pmc_init(void)1594 pmc_init(void)
1595 {
1596 int error, pmc_mod_id;
1597 unsigned int n;
1598 uint32_t abi_version;
1599 struct module_stat pmc_modstat;
1600 struct pmc_op_getcpuinfo op_cpu_info;
1601
1602 if (pmc_syscall != -1) /* already inited */
1603 return (0);
1604
1605 /* retrieve the system call number from the KLD */
1606 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0)
1607 return (-1);
1608
1609 pmc_modstat.version = sizeof(struct module_stat);
1610 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0)
1611 return (-1);
1612
1613 pmc_syscall = pmc_modstat.data.intval;
1614
1615 /* check the kernel module's ABI against our compiled-in version */
1616 abi_version = PMC_VERSION;
1617 if (PMC_CALL(PMC_OP_GETMODULEVERSION, &abi_version) < 0)
1618 return (pmc_syscall = -1);
1619
1620 /* ignore patch & minor numbers for the comparison */
1621 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) {
1622 errno = EPROGMISMATCH;
1623 return (pmc_syscall = -1);
1624 }
1625
1626 bzero(&op_cpu_info, sizeof(op_cpu_info));
1627 if (PMC_CALL(PMC_OP_GETCPUINFO, &op_cpu_info) < 0)
1628 return (pmc_syscall = -1);
1629
1630 cpu_info.pm_cputype = op_cpu_info.pm_cputype;
1631 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu;
1632 cpu_info.pm_npmc = op_cpu_info.pm_npmc;
1633 cpu_info.pm_nclass = op_cpu_info.pm_nclass;
1634 for (n = 0; n < op_cpu_info.pm_nclass; n++)
1635 memcpy(&cpu_info.pm_classes[n], &op_cpu_info.pm_classes[n],
1636 sizeof(cpu_info.pm_classes[n]));
1637
1638 pmc_class_table = calloc(PMC_CLASS_TABLE_SIZE,
1639 sizeof(struct pmc_class_descr *));
1640
1641 if (pmc_class_table == NULL)
1642 return (-1);
1643
1644 /*
1645 * Get soft events list.
1646 */
1647 soft_event_info.pm_class = PMC_CLASS_SOFT;
1648 if (PMC_CALL(PMC_OP_GETDYNEVENTINFO, &soft_event_info) < 0)
1649 return (pmc_syscall = -1);
1650
1651 /* Map soft events to static list. */
1652 for (n = 0; n < soft_event_info.pm_nevent; n++) {
1653 soft_event_table[n].pm_ev_name =
1654 soft_event_info.pm_events[n].pm_ev_name;
1655 soft_event_table[n].pm_ev_code =
1656 soft_event_info.pm_events[n].pm_ev_code;
1657 }
1658 soft_class_table_descr.pm_evc_event_table_size = \
1659 soft_event_info.pm_nevent;
1660 soft_class_table_descr.pm_evc_event_table = \
1661 soft_event_table;
1662
1663 /*
1664 * Fill in the class table.
1665 */
1666 n = 0;
1667 for (unsigned i = 0; i < PMC_CLASS_TABLE_SIZE; i++) {
1668 switch (cpu_info.pm_classes[i].pm_class) {
1669 #if defined(__amd64__) || defined(__i386__)
1670 case PMC_CLASS_TSC:
1671 pmc_class_table[n++] = &tsc_class_table_descr;
1672 break;
1673
1674 case PMC_CLASS_RAPL:
1675 pmc_class_table[n++] = &rapl_class_table_descr;
1676 break;
1677
1678 case PMC_CLASS_K8:
1679 pmc_class_table[n++] = &k8_class_table_descr;
1680 break;
1681
1682 case PMC_CLASS_IBS:
1683 pmc_class_table[n++] = &ibs_class_table_descr;
1684 break;
1685 #endif
1686
1687 case PMC_CLASS_SOFT:
1688 pmc_class_table[n++] = &soft_class_table_descr;
1689 break;
1690
1691 #if defined(__arm__)
1692 case PMC_CLASS_ARMV7:
1693 switch (cpu_info.pm_cputype) {
1694 case PMC_CPU_ARMV7_CORTEX_A8:
1695 pmc_class_table[n++] =
1696 &cortex_a8_class_table_descr;
1697 break;
1698 case PMC_CPU_ARMV7_CORTEX_A9:
1699 pmc_class_table[n++] =
1700 &cortex_a9_class_table_descr;
1701 break;
1702 default:
1703 errno = ENXIO;
1704 return (pmc_syscall = -1);
1705 }
1706 break;
1707 #endif
1708
1709 #if defined(__aarch64__)
1710 case PMC_CLASS_ARMV8:
1711 switch (cpu_info.pm_cputype) {
1712 case PMC_CPU_ARMV8_CORTEX_A53:
1713 pmc_class_table[n++] =
1714 &cortex_a53_class_table_descr;
1715 break;
1716 case PMC_CPU_ARMV8_CORTEX_A57:
1717 pmc_class_table[n++] =
1718 &cortex_a57_class_table_descr;
1719 break;
1720 case PMC_CPU_ARMV8_CORTEX_A76:
1721 pmc_class_table[n++] =
1722 &cortex_a76_class_table_descr;
1723 break;
1724 default:
1725 errno = ENXIO;
1726 return (pmc_syscall = -1);
1727 }
1728 break;
1729
1730 case PMC_CLASS_DMC620_PMU_CD2:
1731 pmc_class_table[n++] =
1732 &dmc620_pmu_cd2_class_table_descr;
1733 break;
1734
1735 case PMC_CLASS_DMC620_PMU_C:
1736 pmc_class_table[n++] = &dmc620_pmu_c_class_table_descr;
1737 break;
1738
1739 case PMC_CLASS_CMN600_PMU:
1740 pmc_class_table[n++] = &cmn600_pmu_class_table_descr;
1741 break;
1742 #endif
1743
1744 #if defined(__powerpc__)
1745 case PMC_CLASS_PPC7450:
1746 pmc_class_table[n++] = &ppc7450_class_table_descr;
1747 break;
1748
1749 case PMC_CLASS_PPC970:
1750 pmc_class_table[n++] = &ppc970_class_table_descr;
1751 break;
1752
1753 case PMC_CLASS_E500:
1754 pmc_class_table[n++] = &e500_class_table_descr;
1755 break;
1756 #endif
1757
1758 default:
1759 #if defined(DEBUG)
1760 printf("pm_class: 0x%x\n",
1761 cpu_info.pm_classes[i].pm_class);
1762 #endif
1763 break;
1764 }
1765 }
1766
1767 #define PMC_MDEP_INIT(C) pmc_mdep_event_aliases = C##_aliases
1768
1769 /* Configure the event name parser. */
1770 switch (cpu_info.pm_cputype) {
1771 #if defined(__amd64__) || defined(__i386__)
1772 case PMC_CPU_AMD_K8:
1773 PMC_MDEP_INIT(k8);
1774 break;
1775 #endif
1776 case PMC_CPU_GENERIC:
1777 PMC_MDEP_INIT(generic);
1778 break;
1779 #if defined(__arm__)
1780 case PMC_CPU_ARMV7_CORTEX_A8:
1781 PMC_MDEP_INIT(cortex_a8);
1782 break;
1783 case PMC_CPU_ARMV7_CORTEX_A9:
1784 PMC_MDEP_INIT(cortex_a9);
1785 break;
1786 #endif
1787 #if defined(__aarch64__)
1788 case PMC_CPU_ARMV8_CORTEX_A53:
1789 PMC_MDEP_INIT(cortex_a53);
1790 break;
1791 case PMC_CPU_ARMV8_CORTEX_A57:
1792 PMC_MDEP_INIT(cortex_a57);
1793 break;
1794 case PMC_CPU_ARMV8_CORTEX_A76:
1795 PMC_MDEP_INIT(cortex_a76);
1796 break;
1797 #endif
1798 #if defined(__powerpc__)
1799 case PMC_CPU_PPC_7450:
1800 PMC_MDEP_INIT(ppc7450);
1801 break;
1802 case PMC_CPU_PPC_970:
1803 PMC_MDEP_INIT(ppc970);
1804 break;
1805 case PMC_CPU_PPC_E500:
1806 PMC_MDEP_INIT(e500);
1807 break;
1808 #endif
1809 default:
1810 /*
1811 * Some kind of CPU this version of the library knows nothing
1812 * about. This shouldn't happen since the abi version check
1813 * should have caught this.
1814 */
1815 #if defined(__amd64__) || defined(__i386__) || defined(__powerpc64__)
1816 break;
1817 #endif
1818 errno = ENXIO;
1819 return (pmc_syscall = -1);
1820 }
1821
1822 return (0);
1823 }
1824
1825 const char *
pmc_name_of_capability(enum pmc_caps cap)1826 pmc_name_of_capability(enum pmc_caps cap)
1827 {
1828 int i;
1829
1830 /*
1831 * 'cap' should have a single bit set and should be in
1832 * range.
1833 */
1834 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST ||
1835 cap > PMC_CAP_LAST) {
1836 errno = EINVAL;
1837 return (NULL);
1838 }
1839
1840 i = ffs(cap);
1841 return (pmc_capability_names[i - 1]);
1842 }
1843
1844 const char *
pmc_name_of_class(enum pmc_class pc)1845 pmc_name_of_class(enum pmc_class pc)
1846 {
1847 size_t n;
1848
1849 for (n = 0; n < PMC_TABLE_SIZE(pmc_class_names); n++)
1850 if (pc == pmc_class_names[n].pm_class)
1851 return (pmc_class_names[n].pm_name);
1852
1853 errno = EINVAL;
1854 return (NULL);
1855 }
1856
1857 const char *
pmc_name_of_cputype(enum pmc_cputype cp)1858 pmc_name_of_cputype(enum pmc_cputype cp)
1859 {
1860 size_t n;
1861
1862 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++)
1863 if (cp == pmc_cputype_names[n].pm_cputype)
1864 return (pmc_cputype_names[n].pm_name);
1865
1866 errno = EINVAL;
1867 return (NULL);
1868 }
1869
1870 const char *
pmc_name_of_disposition(enum pmc_disp pd)1871 pmc_name_of_disposition(enum pmc_disp pd)
1872 {
1873 if ((int) pd >= PMC_DISP_FIRST &&
1874 pd <= PMC_DISP_LAST)
1875 return (pmc_disposition_names[pd]);
1876
1877 errno = EINVAL;
1878 return (NULL);
1879 }
1880
1881 const char *
_pmc_name_of_event(enum pmc_event pe,enum pmc_cputype cpu)1882 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
1883 {
1884 const struct pmc_event_descr *ev, *evfence;
1885
1886 ev = evfence = NULL;
1887 if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) {
1888 ev = k8_event_table;
1889 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8);
1890 } else if (pe >= PMC_EV_IBS_FIRST && pe <= PMC_EV_IBS_LAST) {
1891 ev = ibs_event_table;
1892 evfence = ibs_event_table + PMC_EVENT_TABLE_SIZE(ibs);
1893 } else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) {
1894 switch (cpu) {
1895 case PMC_CPU_ARMV7_CORTEX_A8:
1896 ev = cortex_a8_event_table;
1897 evfence = cortex_a8_event_table + PMC_EVENT_TABLE_SIZE(cortex_a8);
1898 break;
1899 case PMC_CPU_ARMV7_CORTEX_A9:
1900 ev = cortex_a9_event_table;
1901 evfence = cortex_a9_event_table + PMC_EVENT_TABLE_SIZE(cortex_a9);
1902 break;
1903 default: /* Unknown CPU type. */
1904 break;
1905 }
1906 } else if (pe >= PMC_EV_ARMV8_FIRST && pe <= PMC_EV_ARMV8_LAST) {
1907 switch (cpu) {
1908 case PMC_CPU_ARMV8_CORTEX_A53:
1909 ev = cortex_a53_event_table;
1910 evfence = cortex_a53_event_table + PMC_EVENT_TABLE_SIZE(cortex_a53);
1911 break;
1912 case PMC_CPU_ARMV8_CORTEX_A57:
1913 ev = cortex_a57_event_table;
1914 evfence = cortex_a57_event_table + PMC_EVENT_TABLE_SIZE(cortex_a57);
1915 break;
1916 case PMC_CPU_ARMV8_CORTEX_A76:
1917 ev = cortex_a76_event_table;
1918 evfence = cortex_a76_event_table + PMC_EVENT_TABLE_SIZE(cortex_a76);
1919 break;
1920 default: /* Unknown CPU type. */
1921 break;
1922 }
1923 } else if (pe >= PMC_EV_CMN600_PMU_FIRST &&
1924 pe <= PMC_EV_CMN600_PMU_LAST) {
1925 ev = cmn600_pmu_event_table;
1926 evfence = cmn600_pmu_event_table +
1927 PMC_EVENT_TABLE_SIZE(cmn600_pmu);
1928 } else if (pe >= PMC_EV_DMC620_PMU_CD2_FIRST &&
1929 pe <= PMC_EV_DMC620_PMU_CD2_LAST) {
1930 ev = dmc620_pmu_cd2_event_table;
1931 evfence = dmc620_pmu_cd2_event_table +
1932 PMC_EVENT_TABLE_SIZE(dmc620_pmu_cd2);
1933 } else if (pe >= PMC_EV_DMC620_PMU_C_FIRST &&
1934 pe <= PMC_EV_DMC620_PMU_C_LAST) {
1935 ev = dmc620_pmu_c_event_table;
1936 evfence = dmc620_pmu_c_event_table +
1937 PMC_EVENT_TABLE_SIZE(dmc620_pmu_c);
1938 } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) {
1939 ev = ppc7450_event_table;
1940 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450);
1941 } else if (pe >= PMC_EV_PPC970_FIRST && pe <= PMC_EV_PPC970_LAST) {
1942 ev = ppc970_event_table;
1943 evfence = ppc970_event_table + PMC_EVENT_TABLE_SIZE(ppc970);
1944 } else if (pe >= PMC_EV_E500_FIRST && pe <= PMC_EV_E500_LAST) {
1945 ev = e500_event_table;
1946 evfence = e500_event_table + PMC_EVENT_TABLE_SIZE(e500);
1947 } else if (pe == PMC_EV_TSC_TSC) {
1948 ev = tsc_event_table;
1949 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc);
1950 } else if (pe >= PMC_EV_RAPL_FIRST && pe <= PMC_EV_RAPL_LAST) {
1951 ev = rapl_event_table;
1952 evfence = rapl_event_table + PMC_EVENT_TABLE_SIZE(rapl);
1953 } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) {
1954 ev = soft_event_table;
1955 evfence = soft_event_table + soft_event_info.pm_nevent;
1956 }
1957
1958 for (; ev != evfence; ev++)
1959 if (pe == ev->pm_ev_code)
1960 return (ev->pm_ev_name);
1961
1962 return (NULL);
1963 }
1964
1965 const char *
pmc_name_of_event(enum pmc_event pe)1966 pmc_name_of_event(enum pmc_event pe)
1967 {
1968 const char *n;
1969
1970 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL)
1971 return (n);
1972
1973 errno = EINVAL;
1974 return (NULL);
1975 }
1976
1977 const char *
pmc_name_of_mode(enum pmc_mode pm)1978 pmc_name_of_mode(enum pmc_mode pm)
1979 {
1980 if ((int) pm >= PMC_MODE_FIRST &&
1981 pm <= PMC_MODE_LAST)
1982 return (pmc_mode_names[pm]);
1983
1984 errno = EINVAL;
1985 return (NULL);
1986 }
1987
1988 const char *
pmc_name_of_state(enum pmc_state ps)1989 pmc_name_of_state(enum pmc_state ps)
1990 {
1991 if ((int) ps >= PMC_STATE_FIRST &&
1992 ps <= PMC_STATE_LAST)
1993 return (pmc_state_names[ps]);
1994
1995 errno = EINVAL;
1996 return (NULL);
1997 }
1998
1999 int
pmc_ncpu(void)2000 pmc_ncpu(void)
2001 {
2002 if (pmc_syscall == -1) {
2003 errno = ENXIO;
2004 return (-1);
2005 }
2006
2007 return (cpu_info.pm_ncpu);
2008 }
2009
2010 int
pmc_npmc(int cpu)2011 pmc_npmc(int cpu)
2012 {
2013 if (pmc_syscall == -1) {
2014 errno = ENXIO;
2015 return (-1);
2016 }
2017
2018 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) {
2019 errno = EINVAL;
2020 return (-1);
2021 }
2022
2023 return (cpu_info.pm_npmc);
2024 }
2025
2026 int
pmc_pmcinfo(int cpu,struct pmc_pmcinfo ** ppmci)2027 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci)
2028 {
2029 int nbytes, npmc;
2030 struct pmc_op_getpmcinfo *pmci;
2031
2032 if ((npmc = pmc_npmc(cpu)) < 0)
2033 return (-1);
2034
2035 nbytes = sizeof(struct pmc_op_getpmcinfo) +
2036 npmc * sizeof(struct pmc_info);
2037
2038 if ((pmci = calloc(1, nbytes)) == NULL)
2039 return (-1);
2040
2041 pmci->pm_cpu = cpu;
2042
2043 if (PMC_CALL(PMC_OP_GETPMCINFO, pmci) < 0) {
2044 free(pmci);
2045 return (-1);
2046 }
2047
2048 /* kernel<->library, library<->userland interfaces are identical */
2049 *ppmci = (struct pmc_pmcinfo *) pmci;
2050 return (0);
2051 }
2052
2053 int
pmc_read(pmc_id_t pmc,pmc_value_t * value)2054 pmc_read(pmc_id_t pmc, pmc_value_t *value)
2055 {
2056 struct pmc_op_pmcrw pmc_read_op;
2057
2058 pmc_read_op.pm_pmcid = pmc;
2059 pmc_read_op.pm_flags = PMC_F_OLDVALUE;
2060 pmc_read_op.pm_value = -1;
2061
2062 if (PMC_CALL(PMC_OP_PMCRW, &pmc_read_op) < 0)
2063 return (-1);
2064
2065 *value = pmc_read_op.pm_value;
2066 return (0);
2067 }
2068
2069 int
pmc_release(pmc_id_t pmc)2070 pmc_release(pmc_id_t pmc)
2071 {
2072 struct pmc_op_simple pmc_release_args;
2073
2074 pmc_release_args.pm_pmcid = pmc;
2075 return (PMC_CALL(PMC_OP_PMCRELEASE, &pmc_release_args));
2076 }
2077
2078 int
pmc_rw(pmc_id_t pmc,pmc_value_t newvalue,pmc_value_t * oldvaluep)2079 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep)
2080 {
2081 struct pmc_op_pmcrw pmc_rw_op;
2082
2083 pmc_rw_op.pm_pmcid = pmc;
2084 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE;
2085 pmc_rw_op.pm_value = newvalue;
2086
2087 if (PMC_CALL(PMC_OP_PMCRW, &pmc_rw_op) < 0)
2088 return (-1);
2089
2090 *oldvaluep = pmc_rw_op.pm_value;
2091 return (0);
2092 }
2093
2094 int
pmc_set(pmc_id_t pmc,pmc_value_t value)2095 pmc_set(pmc_id_t pmc, pmc_value_t value)
2096 {
2097 struct pmc_op_pmcsetcount sc;
2098
2099 sc.pm_pmcid = pmc;
2100 sc.pm_count = value;
2101
2102 if (PMC_CALL(PMC_OP_PMCSETCOUNT, &sc) < 0)
2103 return (-1);
2104 return (0);
2105 }
2106
2107 int
pmc_start(pmc_id_t pmc)2108 pmc_start(pmc_id_t pmc)
2109 {
2110 struct pmc_op_simple pmc_start_args;
2111
2112 pmc_start_args.pm_pmcid = pmc;
2113 return (PMC_CALL(PMC_OP_PMCSTART, &pmc_start_args));
2114 }
2115
2116 int
pmc_stop(pmc_id_t pmc)2117 pmc_stop(pmc_id_t pmc)
2118 {
2119 struct pmc_op_simple pmc_stop_args;
2120
2121 pmc_stop_args.pm_pmcid = pmc;
2122 return (PMC_CALL(PMC_OP_PMCSTOP, &pmc_stop_args));
2123 }
2124
2125 int
pmc_width(pmc_id_t pmcid,uint32_t * width)2126 pmc_width(pmc_id_t pmcid, uint32_t *width)
2127 {
2128 unsigned int i;
2129 enum pmc_class cl;
2130
2131 cl = PMC_ID_TO_CLASS(pmcid);
2132 for (i = 0; i < cpu_info.pm_nclass; i++)
2133 if (cpu_info.pm_classes[i].pm_class == cl) {
2134 *width = cpu_info.pm_classes[i].pm_width;
2135 return (0);
2136 }
2137 errno = EINVAL;
2138 return (-1);
2139 }
2140
2141 int
pmc_write(pmc_id_t pmc,pmc_value_t value)2142 pmc_write(pmc_id_t pmc, pmc_value_t value)
2143 {
2144 struct pmc_op_pmcrw pmc_write_op;
2145
2146 pmc_write_op.pm_pmcid = pmc;
2147 pmc_write_op.pm_flags = PMC_F_NEWVALUE;
2148 pmc_write_op.pm_value = value;
2149 return (PMC_CALL(PMC_OP_PMCRW, &pmc_write_op));
2150 }
2151
2152 int
pmc_writelog(uint32_t userdata)2153 pmc_writelog(uint32_t userdata)
2154 {
2155 struct pmc_op_writelog wl;
2156
2157 wl.pm_userdata = userdata;
2158 return (PMC_CALL(PMC_OP_WRITELOG, &wl));
2159 }
2160