| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 119 return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) && in constrainCopyLikeIntrin()
120 RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI); in constrainCopyLikeIntrin()
139 return RBI.constrainGenericRegister(DstReg, *RC, *MRI); in selectCOPY()
144 if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI)) in selectCOPY()
202 if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI)) in selectCOPY()
216 RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI); in selectCOPY()
237 return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, *MRI); in selectCOPY_SCC_VCC()
259 return RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI); in selectCOPY_VCC_SCC()
331 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI)) in selectPHI()
337 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI); in selectPHI()
[all …]
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| H A D | AMDGPURegisterBankInfo.cpp | 740 constrainGenericRegister(SrcPart, AMDGPU::VGPR_32RegClass, MRI); in buildReadFirstLane()
1878 return constrainGenericRegister(DstReg, AMDGPU::VGPR_32RegClass, MRI) && in buildVCopy()
1879 constrainGenericRegister(SrcReg, AMDGPU::SReg_32RegClass, MRI); in buildVCopy()
1898 return constrainGenericRegister(SrcReg, AMDGPU::SReg_64RegClass, MRI) && in buildVCopy()
1899 constrainGenericRegister(DstReg, AMDGPU::VReg_64RegClass, MRI); in buildVCopy()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 274 RBI.constrainGenericRegister(Reg, *RC, MRI); in selectDebugInstr()
348 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
807 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || in selectTurnIntoCOPY()
808 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectTurnIntoCOPY()
870 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || in selectTruncOrPtrToInt()
871 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectTruncOrPtrToInt()
980 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || in selectAnyext()
981 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectAnyext()
1107 RBI.constrainGenericRegister( in selectFCmp()
1233 if (!RBI.constrainGenericRegister(CarryInReg, *DstRC, MRI)) in selectUAddSub()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 945 RBI.constrainGenericRegister(I.getOperand(0).getReg(), *To, MRI); in copySubReg()
1008 RBI.constrainGenericRegister(Reg, *RC, MRI); in selectDebugInstr()
1087 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
2195 RBI.constrainGenericRegister(NewSrc, AArch64::GPR64RegClass, MRI); in preISelLower()
2447 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI); in earlySelect()
2450 RBI.constrainGenericRegister(DefReg, AArch64::GPR32RegClass, MRI); in earlySelect()
2616 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); in select()
2807 return RBI.constrainGenericRegister(DefReg, FPRRC, MRI); in select()
2820 if (!RBI.constrainGenericRegister(DefReg, FPRRC, MRI)) { in select()
2904 RBI.constrainGenericRegister(I.getOperand(0).getReg(), in select()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVInstructionSelector.cpp | 707 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI); in select()
1021 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) { in selectCopy()
1042 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) { in selectImplicitDef()
1054 RBI.constrainGenericRegister(DstReg, RISCV::GPRRegClass, *MRI); in materializeImm()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterBankInfo.h | 666 constrainGenericRegister(Register Reg, const TargetRegisterClass &RC,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 112 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
430 return RBI.constrainGenericRegister(DestReg, *DefRC, MRI); in select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 225 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
1178 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in select()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterBankInfo.cpp | 131 const TargetRegisterClass *RegisterBankInfo::constrainGenericRegister( in constrainGenericRegister() function in RegisterBankInfo
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 145 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 50 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) in constrainRegToClass()
|