Searched refs:composeSubRegIndices (Results 1 – 12 of 12) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetRegisterInfo.cpp | 385 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); in getCommonSuperRegClass() 394 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); in getCommonSuperRegClass()
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| H A D | RegisterCoalescer.cpp | 433 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(), in INITIALIZE_PASS_DEPENDENCY() 591 return TRI.composeSubRegIndices(SrcIdx, SrcSub) == in isCoalescable() 592 TRI.composeSubRegIndices(DstIdx, DstSub); in isCoalescable() 1382 unsigned NewDstIdx = TRI->composeSubRegIndices(CP.getSrcIdx(), DefSubIdx); in reMaterializeTrivialDef() 1930 unsigned SubUseIdx = TRI->composeSubRegIndices(SubIdx, MO.getSubReg()); in updateRegDefsUses() 2717 TRI->composeSubRegIndices(SubIdx, MO.getSubReg())); in computeWriteLanes() 3180 unsigned S = TRI->composeSubRegIndices(SubIdx, MO.getSubReg()); in usesLanes()
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| H A D | DetectDeadLanes.cpp | 93 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); in isCrossCopy()
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| H A D | TailDuplicator.cpp | 457 TRI->composeSubRegIndices(VI->second.SubReg, MO.getSubReg())); in duplicateInstruction()
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| H A D | MachineOperand.cpp | 86 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
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| H A D | PeepholeOptimizer.cpp | 2002 TRI->composeSubRegIndices(RegSeqInput.SubReg, ReverseDefCompose); in getNextSourceFromRegSequence()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 728 unsigned composeSubRegIndices(unsigned a, unsigned b) const { in composeSubRegIndices() function
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 74 Copy.DefSubReg = TRI.composeSubRegIndices(DefSubReg, SubReg); in getWithSubReg()
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| H A D | AMDGPUInstructionSelector.cpp | 350 unsigned ComposedSubIdx = TRI.composeSubRegIndices(MO.getSubReg(), SubIdx); in getSubOperand64()
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| H A D | SIInstrInfo.cpp | 5911 unsigned NewSubIdx = RI.composeSubRegIndices(SuperReg.getSubReg(), SubIdx); in buildExtractSubReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 2689 SubRegIdx = TRI->composeSubRegIndices(SubRegIdx, in decomposeSubvectorInsertExtractToSubRegs()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Testing/Demangle/ |
| H A D | DemangleTestCases.inc | 13204 …egisterInfo20composeSubRegIndicesEjj", "llvm::X86GenRegisterInfo::composeSubRegIndices(unsigned in… 13672 …egisterInfo20composeSubRegIndicesEjj", "llvm::ARMGenRegisterInfo::composeSubRegIndices(unsigned in… 20646 …egisterInfo20composeSubRegIndicesEjj", "llvm::TargetRegisterInfo::composeSubRegIndices(unsigned in…
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