Searched refs:code_properties (Results 1 – 7 of 7) sorted by relevance
33 printBitField<FLD_T(code_properties),\40 parseBitField<FLD_T(code_properties),\
49 uint32_t code_properties = 0; member
488 const MCExpr *CodeProps = MCConstantExpr::create(code_properties, Ctx); in EmitKernelCodeT()497 OS.emitIntValue(code_properties, /*Size=*/4); in EmitKernelCodeT()
1475 KernelCode.code_properties |= AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32; in initDefaultAMDKernelCodeT()
1591 Out.code_properties |= AMD_CODE_PROPERTY_IS_PTR64; in getAmdKernelCode()1595 AMD_HSA_BITS_SET(Out.code_properties, AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE, in getAmdKernelCode()1600 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER; in getAmdKernelCode()1604 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR; in getAmdKernelCode()1607 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR; in getAmdKernelCode()1610 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR; in getAmdKernelCode()1613 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID; in getAmdKernelCode()1616 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT; in getAmdKernelCode()1619 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE; in getAmdKernelCode()1622 Out.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED; in getAmdKernelCode()
562 uint32_t code_properties; member
6316 if (C.code_properties & AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32) { in ParseAMDKernelCodeTValue()