Searched refs:canCombine (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 981 static bool canCombine(MachineBasicBlock &MBB, MachineOperand &MO, in canCombine() function
1024 canCombine(MBB, CurrentInstr->getOperand(1), AccumulatorOpcode)) { in getAccumulatorChain()
1031 canCombine(MBB, CurrentInstr->getOperand(1))) in getAccumulatorChain()
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| H A D | CodeGenPrepare.cpp | 8192 bool canCombine(const Instruction *Use) { return isa<StoreInst>(Use); } in canCombine() function in __anon1d600f581b11::VectorPromoteHelper
8201 assert(canCombine(ToBeCombined) && "Unsupported instruction to combine"); in recordCombineInstruction()
8305 if (VPH.canCombine(ToBePromoted)) { in optimizeExtractElementInst()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 6592 static bool canCombine(MachineBasicBlock &MBB, MachineOperand &MO, in canCombine() function
6627 return canCombine(MBB, MO, MulOpc, ZeroReg, true); in canCombineWithMUL()
6634 return canCombine(MBB, MO, MulOpc); in canCombineWithFMUL()
6777 if (canCombine(MBB, Root.getOperand(Operand), Opcode)) { in getMaddPatterns()
7382 if (canCombine(MBB, Root.getOperand(2), AArch64::ADDWrr) || in getMiscPatterns()
7383 canCombine(MBB, Root.getOperand(2), AArch64::ADDSWrr) || in getMiscPatterns()
7384 canCombine(MBB, Root.getOperand(2), AArch64::ADDXrr) || in getMiscPatterns()
7385 canCombine(MBB, Root.getOperand(2), AArch64::ADDSXrr)) { in getMiscPatterns()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 2482 static const MachineInstr *canCombine(const MachineBasicBlock &MBB, in canCombine() function
2506 const MachineInstr *ShiftMI = canCombine(MBB, MO, RISCV::SLLI); in canCombineShiftIntoShXAdd()
2557 const MachineInstr *AddMI = canCombine(MBB, Root.getOperand(2), RISCV::ADD); in getSHXADDPatterns()
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