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Searched refs:buildSelect (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2352 B.buildSelect(Dst, CmpRes, PtrLo32, SegmentNull.getReg(0)); in legalizeAddrSpaceCast()
2386 B.buildSelect(Dst, CmpRes, BuildPtr, FlatNull); in legalizeAddrSpaceCast()
2442 B.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2); in legalizeFroundeven()
2468 auto Add = B.buildSelect(S64, And, One, Zero); in legalizeFceil()
2549 auto Tmp1 = B.buildSelect(S64, ExpLt0, SignBit64, Tmp0); in legalizeIntrinsicTrunc()
2550 B.buildSelect(MI.getOperand(0).getReg(), ExpGt51, Src, Tmp1); in legalizeIntrinsicTrunc()
3279 B.buildSelect(F32, IsLtSmallestNormal, Scale32, One, Flags); in getScaledLogInput()
3328 B.buildSelect(Ty, IsLtSmallestNormal, ThirtyTwo, Zero, Flags); in legalizeFlog2()
3432 R = B.buildSelect(Ty, IsFinite, R, Y, Flags).getReg(0); in legalizeFlogCommon()
3439 auto Shift = B.buildSelect(Ty, IsScaled, ShiftK, Zero, Flags); in legalizeFlogCommon()
[all …]
H A DAMDGPURegisterBankInfo.cpp144 B.buildSelect(DstReg, SrcReg, True, False); in applyBank()
1981 auto S = B.buildSelect(EltTy, Cmp, in foldExtractEltToCmpSelect()
2086 Register Select = B.buildSelect(EltTy, Cmp, Op0, Op1).getReg(0); in foldInsertEltToCmpSelect()
2356 B.buildSelect(DefRegs[0], CondRegs[0], Src1Regs[0], Src2Regs[0]); in applyMappingImpl()
2357 B.buildSelect(DefRegs[1], CondRegs[0], Src1Regs[1], Src2Regs[1]); in applyMappingImpl()
2774 B.buildSelect(DefRegs[0], SrcReg, True, False); in applyMappingImpl()
2777 auto Sel = B.buildSelect(SelType, SrcReg, True, False); in applyMappingImpl()
2781 B.buildSelect(DstReg, SrcReg, True, False); in applyMappingImpl()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp1598 MIRBuilder.buildSelect(Dst, CmpHEQ, CmpLU, CmpH); in narrowScalar()
5341 auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL); in narrowScalarShift()
5342 auto Hi = MIRBuilder.buildSelect( in narrowScalarShift()
5343 HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL)); in narrowScalarShift()
5369 auto Lo = MIRBuilder.buildSelect( in narrowScalarShift()
5370 HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL)); in narrowScalarShift()
5372 auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL); in narrowScalarShift()
6265 auto Select = MIRBuilder.buildSelect(NarrowTy, in narrowScalarSelect()
6271 auto Select = MIRBuilder.buildSelect( in narrowScalarSelect()
6307 B.buildSelect(DstReg, HiIsZero, HiIsZeroCTLZ, HiCTLZ); in narrowScalarCTLZ()
[all …]
H A DMachineIRBuilder.cpp927 MachineIRBuilder::buildSelect(const DstOp &Res, const SrcOp &Tst, in buildSelect() function in MachineIRBuilder
H A DCombinerHelper.cpp3672 Builder.buildSelect(Dst, SelectCond, FoldTrue, FoldFalse, MI.getFlags()); in applyFoldBinOpIntoSelect()
5328 return MIB.buildSelect(Ty, IsOne, LHS, Q); in buildUDivUsingMul()
5542 AShr = Builder.buildSelect(Ty, IsOneOrMinusOne, LHS, AShr); in applySDivByPow2()
5548 Builder.buildSelect(MI.getOperand(0).getReg(), IsNeg, Neg, AShr); in applySDivByPow2()
H A DIRTranslator.cpp1521 MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i], Flags); in translateSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp648 MIB.buildSelect(Dst, Src, SplatTrue, SplatZero); in legalizeExt()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVBuiltins.cpp433 return MIRBuilder.buildSelect(ReturnRegister, SourceRegister, TrueConst, in buildSelectInst()
1412 MIRBuilder.buildSelect(SelectionResult, CompareRegister, Extracted, in genWorkgroupQuery()
1873 MIRBuilder.buildSelect(Call->ReturnRegister, Call->Arguments[0], in generateSelectInst()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h1321 MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,