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Searched refs:buildSExtInReg (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelperCasts.cpp52 B.buildSExtInReg(Dst, Src, TruncWidth); in matchSextOfTrunc()
410 B.buildSExtInReg(Dst, Src, RootWidth); in matchRedundantSextInReg()
H A DMachineIRBuilder.cpp539 return buildSExtInReg(Res, Op, 1); in buildBoolExtInReg()
H A DLegalizerHelper.cpp2653 ExtResult = MIRBuilder.buildSExtInReg(WideTy, Mul, SrcBitWidth); in widenScalarMulo()
4080 MIRBuilder.buildSExtInReg(LoadReg, NewLoad, MemSizeInBits); in lowerLoad()
9436 MaskElt = MIRBuilder.buildSExtInReg(MaskTy, MaskElt, 1).getReg(0); in lowerSelect()
H A DCombinerHelper.cpp3286 Builder.buildSExtInReg(MI.getOperand(0).getReg(), Src, Size - ShiftAmt); in applyAshShlToSextInreg()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegBankLegalizeHelper.cpp183 auto Lo = B.buildSExtInReg(SgprRB_S32, PackedS32, 16); in unpackSExt()
373 Lo = B.buildSExtInReg(VgprRB_S32, Freeze, Amt).getReg(0); in lowerSplitTo32SExtInReg()
381 Hi = B.buildSExtInReg(VgprRB_S32, Op1.getReg(1), Amt - 32).getReg(0); in lowerSplitTo32SExtInReg()
H A DAMDGPURegisterBankInfo.cpp1100 B.buildSExtInReg(MI.getOperand(0), WideLoad, MemSize); in applyMappingLoad()
1754 auto ExtLo = B.buildSExtInReg(S32, Bitcast, 16); in unpackV2S16ToS32()
2680 B.buildSExtInReg(DstRegs[0], Freeze, Amt); in applyMappingImpl()
2688 B.buildSExtInReg(DstRegs[1], DstRegs[0], Amt - 32); in applyMappingImpl()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h222 Builder.buildSExtInReg(DstReg, TruncSrc, SizeInBits); in tryCombineSExt()
H A DMachineIRBuilder.h703 MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) { in buildSExtInReg() function
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp1351 auto DstSext = MIRBuilder.buildSExtInReg(sXLen, DstALU, 32); in legalizeCustom()