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Searched refs:buildConstant (Results 1 – 25 of 38) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp273 PadReg = MIRBuilder.buildConstant(GCDTy, 0).getReg(0); in buildLCMMergePieces()
281 MIRBuilder.buildConstant(LLT::scalar(64), GCDTy.getSizeInBits() - 1); in buildLCMMergePieces()
322 AllPadReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0); in buildLCMMergePieces()
881 MIRBuilder.buildXor(ValLLT, MIRBuilder.buildConstant(ValLLT, -1), Val) in createAtomicLibcall()
885 MIRBuilder.buildSub(ValLLT, MIRBuilder.buildConstant(ValLLT, 0), Val) in createAtomicLibcall()
1148 .buildICmp(ICmpPred, Res, Temp, MIRBuilder.buildConstant(TempLLT, 0)) in createFCMPLibcall()
1251 auto DefValue = MIRBuilder.buildConstant(LLT::scalar(PtrSize), -1LL); in createResetStateLibcall()
1537 auto K = MIRBuilder.buildConstant(NarrowTy, in narrowScalar()
1547 auto K = MIRBuilder.buildConstant( in narrowScalar()
1813 auto Zero = MIRBuilder.buildConstant(NarrowTy, 0); in narrowScalar()
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H A DCSEMIRBuilder.cpp198 return buildConstant(DstOps[0], Cst->front()); in buildInstr()
240 return buildConstant(DstOps[0], *Cst); in buildInstr()
271 return buildConstant(Dst, *MaybeCst); in buildInstr()
297 return buildConstant(DstOps[0], (*MaybeCsts)[0]); in buildInstr()
303 buildConstant(VecTy.getScalarType(), Cst).getReg(0)); in buildInstr()
334 MachineInstrBuilder CSEMIRBuilder::buildConstant(const DstOp &Res, in buildConstant() function in CSEMIRBuilder
338 return MachineIRBuilder::buildConstant(Res, Val); in buildConstant()
343 return buildSplatBuildVector(Res, buildConstant(Ty.getElementType(), Val)); in buildConstant()
357 MachineInstrBuilder NewMIB = MachineIRBuilder::buildConstant(Res, Val); in buildConstant()
H A DCombinerHelperCompares.cpp50 B.buildConstant(Dst, getICmpTrueVal(getTargetLowering(), in constantFoldICmp()
54 B.buildConstant(Dst, 0); in constantFoldICmp()
81 B.buildConstant(Dst, getICmpTrueVal(getTargetLowering(), in constantFoldFCmp()
85 B.buildConstant(Dst, 0); in constantFoldFCmp()
H A DCombinerHelper.cpp98 auto Base = MIB.buildConstant(Ty, Ty.getScalarSizeInBits() - 1); in buildLogBase2()
1521 auto NewCst = Builder.buildConstant(MRI.getType(MatchInfo.Offset), in applyCombineIndexedLoadStore()
1682 auto True = Builder.buildConstant( in applyOptBrCondByInvertingCond()
1836 auto NewOffset = MIB.buildConstant(OffsetTy, MatchInfo.Imm); in applyPtrAddImmedChain()
1904 Builder.buildConstant(MI.getOperand(0), 0); in applyShiftImmedChain()
1914 Register NewImm = Builder.buildConstant(ImmTy, Imm).getReg(0); in applyShiftImmedChain()
2013 Register Const = Builder.buildConstant(ShlType, MatchInfo.ValSum).getReg(0); in applyShiftOfShiftedLogic()
2094 auto ShiftCst = MIB.buildConstant(ShiftTy, ShiftVal); in applyCombineMulToShl()
2118 auto NegCst = B.buildConstant(Ty, -Imm); in matchCombineSubToAdd()
2177 auto ShiftAmt = Builder.buildConstant(ExtSrcTy, ShiftAmtVal); in applyCombineShlOfExtend()
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H A DMachineIRBuilder.cpp223 auto Cst = buildConstant(ValueTy, Value); in materializePtrAdd()
233 buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits)); in buildMaskLowPtrBits()
317 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, in buildConstant() function in MachineIRBuilder
342 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, in buildConstant() function in MachineIRBuilder
347 return buildConstant(Res, *CI); in buildConstant()
380 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, in buildConstant() function in MachineIRBuilder
383 return buildConstant(Res, *CI); in buildConstant()
465 auto ConstOffset = buildConstant(OffsetTy, Offset); in buildLoadFromOffset()
592 auto Mask = buildConstant( in buildZExtInReg()
738 TmpVec.push_back(buildConstant(EltTy, Op)); in buildBuildVectorConstant()
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H A DIRTranslator.cpp878 auto FirstCst = MIB.buildConstant(SwitchTy, JTH.First); in emitJumpTableHeader()
966 auto Diff = MIB.buildConstant(CmpTy, High - Low); in emitSwitchCase()
1105 Register MinValReg = MIB.buildConstant(SwitchOpTy, B.First).getReg(0); in emitBitTestHeader()
1143 auto RangeCst = MIB.buildConstant(SwitchOpTy, B.Range); in emitBitTestHeader()
1169 MIB.buildConstant(SwitchTy, llvm::countr_zero(B.Mask)); in emitBitTestCase()
1176 MIB.buildConstant(SwitchTy, llvm::countr_one(B.Mask)); in emitBitTestCase()
1181 auto CstOne = MIB.buildConstant(SwitchTy, 1); in emitBitTestCase()
1185 auto CstMask = MIB.buildConstant(SwitchTy, B.Mask); in emitBitTestCase()
1187 auto CstZero = MIB.buildConstant(SwitchTy, 0); in emitBitTestCase()
1646 auto OffsetMIB = MIRBuilder.buildConstant({OffsetTy}, Offset); in translateGetElementPtr()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegBankLegalizeHelper.cpp78 auto Offset = B.buildConstant({PtrRB, OffsetTy}, ByteOffset); in splitLoad()
143 auto True = B.buildConstant({VgprRB, Ty}, TrueExtCst); in lowerVccExtToSel()
144 auto False = B.buildConstant({VgprRB, Ty}, 0); in lowerVccExtToSel()
147 auto True = B.buildConstant({VgprRB_S32}, TrueExtCst); in lowerVccExtToSel()
148 auto False = B.buildConstant({VgprRB_S32}, 0); in lowerVccExtToSel()
175 auto Mask = B.buildConstant(SgprRB_S32, 0x0000ffff); in unpackZExt()
177 auto Hi = B.buildLShr(SgprRB_S32, PackedS32, B.buildConstant(SgprRB_S32, 16)); in unpackZExt()
184 auto Hi = B.buildAShr(SgprRB_S32, PackedS32, B.buildConstant(SgprRB_S32, 16)); in unpackSExt()
191 auto Hi = B.buildLShr(SgprRB_S32, PackedS32, B.buildConstant(SgprRB_S32, 16)); in unpackAExt()
256 auto Amt = B.buildSub(VgprRB_S32, B.buildConstant(SgprRB_S32, 64), Width); in lowerV_BFE()
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H A DAMDGPULegalizerInfo.cpp2299 B.buildConstant(LLT::scalar(64), Offset).getReg(0)); in getSegmentAperture()
2321 B.buildConstant(LLT::scalar(64), StructOffset).getReg(0)); in getSegmentAperture()
2392 auto SegmentNull = B.buildConstant(DstTy, NullVal); in legalizeAddrSpaceCast()
2393 auto FlatNull = B.buildConstant(SrcTy, 0); in legalizeAddrSpaceCast()
2433 auto SegmentNull = B.buildConstant(SrcTy, TM.getNullPointerValue(SrcAS)); in legalizeAddrSpaceCast()
2434 auto FlatNull = B.buildConstant(DstTy, TM.getNullPointerValue(DestAS)); in legalizeAddrSpaceCast()
2458 auto HighAddr = B.buildConstant(S32, AddrHiVal); in legalizeAddrSpaceCast()
2549 auto Const0 = B.buildConstant(S32, FractBits - 32); in extractF64Exponent()
2550 auto Const1 = B.buildConstant(S32, ExpBits); in extractF64Exponent()
2557 return B.buildSub(S32, ExpPart, B.buildConstant(S32, 1023)); in extractF64Exponent()
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H A DAMDGPURegisterBankInfo.cpp142 auto True = B.buildConstant(S32, Opc == AMDGPU::G_SEXT ? -1 : 1); in applyBank()
143 auto False = B.buildConstant(S32, 0); in applyBank()
1207 auto WaveSize = B.buildConstant(LLT::scalar(32), ST.getWavefrontSizeLog2()); in applyMappingDynStackAlloc()
1214 B.buildConstant(LLT::scalar(32), StackAlignMask)); in applyMappingDynStackAlloc()
1266 VOffsetReg = B.buildConstant(S32, 0).getReg(0); in setBufferOffsets()
1267 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0); in setBufferOffsets()
1287 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0); in setBufferOffsets()
1295 VOffsetReg = B.buildConstant(S32, 0).getReg(0); in setBufferOffsets()
1334 SOffsetReg = B.buildConstant(S32, 0).getReg(0); in setBufferOffsets()
1413 Register VIndex = B.buildConstant(S32, 0).getReg(0); in applyMappingSBufferLoad()
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H A DAMDGPUPreLegalizerCombiner.cpp195 auto MinBoundaryDst = B.buildConstant(S32, MinBoundary); in applyClampI64ToI16()
196 auto MaxBoundaryDst = B.buildConstant(S32, MaxBoundary); in applyClampI64ToI16()
H A DAMDGPUCallLowering.cpp225 auto OffsetReg = MIRBuilder.buildConstant(S32, Offset); in getStackAddress()
401 auto OffsetReg = B.buildConstant(LLT::scalar(64), Offset); in lowerParameterPtr()
832 MIRBuilder.buildConstant(InputReg, *Id); in passSpecialInputs()
896 InputReg = MIRBuilder.buildConstant(S32, 0).getReg(0); in passSpecialInputs()
906 Y = MIRBuilder.buildShl(S32, Y, MIRBuilder.buildConstant(S32, 10)).getReg(0); in passSpecialInputs()
916 Z = MIRBuilder.buildShl(S32, Z, MIRBuilder.buildConstant(S32, 20)).getReg(0); in passSpecialInputs()
H A DAMDGPUCombinerHelper.cpp504 Builder.buildConstant(IntDestTy, SelectTrueLog2Val), in matchCombineFmulWithSelectToFldexp()
505 Builder.buildConstant(IntDestTy, SelectFalseLog2Val)); in matchCombineFmulWithSelectToFldexp()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PreLegalizerCombiner.cpp68 MIB.buildConstant(MI.getOperand(0).getReg(), ImmValAPF.bitcastToAPInt()); in applyFConstantToConstant()
113 auto WideZero = Builder.buildConstant(WideTy, 0); in applyICmpRedundantTrunc()
228 B.buildConstant(LLT::scalar(64), -static_cast<int64_t>(MinOffset))); in applyFoldGlobalOffset()
309 Ext2SrcReg = Builder.buildConstant(MRI.getType(Ext1SrcReg), 1) in applyExtAddvToUdotAddv()
331 auto Zeroes = Builder.buildConstant(MidTy, 0)->getOperand(0).getReg(); in applyExtAddvToUdotAddv()
356 Register v8Zeroes = Builder.buildConstant(LLT::fixed_vector(8, 8), 0) in applyExtAddvToUdotAddv()
393 auto Zeroes = Builder.buildConstant(ZeroesLLT, 0)->getOperand(0).getReg(); in applyExtAddvToUdotAddv()
493 Register zeroReg = B.buildConstant(LLT::scalar(64), 0).getReg(0); in applyExtUaddvToUaddlv()
702 B.buildConstant(LLT::scalar(32), OpTySize == 8 ? 1 << 8 : 1 << 16)); in tryToSimplifyUADDO()
704 B.buildConstant(LLT::scalar(32), 0)); in tryToSimplifyUADDO()
H A DAArch64PostLegalizerCombiner.cpp119 auto Elt0 = B.buildExtractVectorElement(Ty, Src, B.buildConstant(s64, 0)); in applyExtractVecEltPairwiseAdd()
120 auto Elt1 = B.buildExtractVectorElement(Ty, Src, B.buildConstant(s64, 1)); in applyExtractVecEltPairwiseAdd()
226 auto Shift = B.buildConstant(LLT::scalar(64), ShiftAmt); in matchAArch64MulConstCombine()
236 B.buildSub(DstReg, B.buildConstant(Ty, 0), Res); in matchAArch64MulConstCombine()
241 B.buildShl(DstReg, Res, B.buildConstant(LLT::scalar(64), TrailingZeroes)); in matchAArch64MulConstCombine()
334 auto Zero = B.buildConstant(NewTy, 0); in applySplitStoreZero128()
336 B.buildConstant(LLT::scalar(64), 8)); in applySplitStoreZero128()
430 Register ZeroVec = B.buildConstant(HalfTy, 0).getReg(0); in applyCombineMulCMLT()
721 auto NewOff = MIB.buildConstant(LLT::scalar(64), SInfo.Offset - BaseOffset); in tryOptimizeConsecStores()
H A DAArch64PostLegalizerLowering.cpp400 MIRBuilder.buildConstant(LLT::scalar(32), MatchInfo.SrcOps[2].getImm()); in applyEXT()
414 auto Cst = MIRBuilder.buildConstant(LLT::scalar(32), 8); in applyFullRev()
457 auto Mask = Builder.buildConstant(IdxTy, VecTy.getNumElements() - 1); in applyNonConstInsert()
459 auto EltSize = Builder.buildConstant(IdxTy, EltTy.getSizeInBytes()); in applyNonConstInsert()
519 auto SrcCst = Builder.buildConstant(LLT::scalar(64), SrcLane); in applyINS()
521 auto DstCst = Builder.buildConstant(LLT::scalar(64), DstLane); in applyINS()
559 auto ImmDef = MIB.buildConstant(LLT::scalar(32), Imm); in applyVAshrLshrImm()
699 auto Cst = MIB.buildConstant(MRI.cloneVirtualRegister(RHS.getReg()), in applyAdjustICmpImmAndPred()
770 auto Lane = B.buildConstant(LLT::scalar(64), MatchInfo.second); in applyDupLane()
1069 auto IdxReg = B.buildConstant(LLT::scalar(64), I); in applyLowerBuildToInsertVecElt()
H A DAArch64LegalizerInfo.cpp1514 auto Cast64 = MIRBuilder.buildConstant(LLT::scalar(64), Amount.zext(64)); in legalizeFunnelShift()
1674 MIB.buildConstant(MI.getOperand(0).getReg(), 0); in legalizeIntrinsic()
1763 MIB.buildConstant(LLT::scalar(64), 0)->getOperand(0).getReg(); in legalizeIntrinsic()
1848 auto ExtCst = MIRBuilder.buildConstant(LLT::scalar(64), Amount); in legalizeShlAshrLshr()
1985 MIRBuilder.buildConstant(IntPtrTy, Alignment.value() - 1); in legalizeVaArg()
1998 auto Size = MIRBuilder.buildConstant(IntPtrTy, alignTo(ValSize, PtrAlign)); in legalizeVaArg()
2092 auto Zeros = MIRBuilder.buildConstant(Dt, 0); in legalizeCTPOP()
2093 auto Ones = MIRBuilder.buildConstant(VTy, 1); in legalizeCTPOP()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCSEMIRBuilder.h105 using MachineIRBuilder::buildConstant;
107 MachineInstrBuilder buildConstant(const DstOp &Res,
H A DLegalizationArtifactCombiner.h108 Builder.buildConstant( in tryCombineAnyExt()
158 auto Mask = Builder.buildConstant(DstTy, ExtMaskVal); in tryCombineZExt()
183 Builder.buildConstant( in tryCombineZExt()
247 Builder.buildConstant( in tryCombineSExt()
275 Builder.buildConstant( in tryCombineTrunc()
406 auto Cnst = Builder.buildConstant(DstTy, 0); in tryFoldImplicitDef()
H A DMachineIRBuilder.h914 virtual MachineInstrBuilder buildConstant(const DstOp &Res,
925 MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
926 MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
1423 return buildExtractVectorElement(Res, Val, buildConstant(IdxTy, Idx)); in buildExtractVectorElementConstant()
1990 auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1); in buildNot()
1998 auto Zero = buildConstant(Dst.getLLTTy(*getMRI()), 0); in buildNeg()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLegalizerInfo.cpp391 MIRBuilder.buildConstant(OriginalResult, in legalizeCustom()
429 auto Zero = MIRBuilder.buildConstant(LLT::scalar(32), 0); in legalizeCustom()
452 MIRBuilder.buildConstant(MI.getOperand(0), in legalizeCustom()
462 auto StatusBitMask = MIRBuilder.buildConstant(FPEnvTy, ARM::FPStatusBits); in legalizeCustom()
465 MIRBuilder.buildConstant(FPEnvTy, ~ARM::FPStatusBits); in legalizeCustom()
476 auto NotModeBitMask = MIRBuilder.buildConstant( in legalizeCustom()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp766 auto ShiftAmt = MIRBuilder.buildConstant(IndexTy, Log2_32(EntrySize)); in legalizeBRJT()
861 MIB.buildLShr(Dst, VLENB, MIB.buildConstant(XLenTy, 3 - Log2)); in legalizeVScale()
864 MIB.buildShl(Dst, VLENB, MIB.buildConstant(XLenTy, Log2 - 3)); in legalizeVScale()
872 MIB.buildMul(Dst, VLENB, MIB.buildConstant(XLenTy, Val / 8)); in legalizeVScale()
875 auto VScale = MIB.buildLShr(XLenTy, VLENB, MIB.buildConstant(XLenTy, 3)); in legalizeVScale()
876 MIB.buildMul(Dst, VScale, MIB.buildConstant(XLenTy, Val)); in legalizeVScale()
900 auto SplatZero = MIB.buildSplatVector(DstTy, MIB.buildConstant(DstEltTy, 0)); in legalizeExt()
902 MIB.buildSplatVector(DstTy, MIB.buildConstant(DstEltTy, ExtTrueVal)); in legalizeExt()
974 auto VL = MIB.buildConstant(XLenTy, -1); in buildDefaultVLOps()
1052 MIB.buildAnd(InterEltTy, ZExtSplatVal, MIB.buildConstant(InterEltTy, 1)); in legalizeSplatVector()
[all …]
H A DRISCVCallLowering.cpp72 auto OffsetReg = MIRBuilder.buildConstant(sXLen, Offset); in getStackAddress()
505 auto Offset = MIRBuilder.buildConstant( in saveVarArgRegisters()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsLegalizerInfo.cpp380 auto C_P2HalfMemSize = MIRBuilder.buildConstant(s32, P2HalfMemSize); in legalizeCustom()
385 auto C_P2Half_InBits = MIRBuilder.buildConstant(s32, P2HalfMemSize * 8); in legalizeCustom()
409 auto C_P2HalfMemSize = MIRBuilder.buildConstant(s32, P2HalfMemSize); in legalizeCustom()
445 auto C_HiMask = MIRBuilder.buildConstant(s32, UINT32_C(0x43300000)); in legalizeCustom()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86LegalizerInfo.cpp841 s8, MIRBuilder.buildLShr(s32, CWD32, MIRBuilder.buildConstant(s8, 9))); in legalizeGETROUNDING()
843 s32, MIRBuilder.buildAnd(s8, Shifted8, MIRBuilder.buildConstant(s8, 6))); in legalizeGETROUNDING()
849 auto LUT = MIRBuilder.buildConstant(s32, 0x2d); in legalizeGETROUNDING()
852 MIRBuilder.buildAnd(s32, LUTShifted, MIRBuilder.buildConstant(s32, 3)); in legalizeGETROUNDING()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp84 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); in getStackAddress()

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