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Searched refs:buildConstant (Results 1 – 25 of 31) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp273 PadReg = MIRBuilder.buildConstant(GCDTy, 0).getReg(0); in buildLCMMergePieces()
281 MIRBuilder.buildConstant(LLT::scalar(64), GCDTy.getSizeInBits() - 1); in buildLCMMergePieces()
322 AllPadReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0); in buildLCMMergePieces()
816 MIRBuilder.buildXor(ValLLT, MIRBuilder.buildConstant(ValLLT, -1), Val) in createAtomicLibcall()
820 MIRBuilder.buildSub(ValLLT, MIRBuilder.buildConstant(ValLLT, 0), Val) in createAtomicLibcall()
1013 auto DefValue = MIRBuilder.buildConstant(LLT::scalar(PtrSize), -1LL); in createResetStateLibcall()
1274 auto K = MIRBuilder.buildConstant(NarrowTy, in narrowScalar()
1284 auto K = MIRBuilder.buildConstant( in narrowScalar()
1555 auto Zero = MIRBuilder.buildConstant(NarrowTy, 0); in narrowScalar()
1661 MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1) in narrowScalar()
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H A DCSEMIRBuilder.cpp192 return buildConstant(DstOps[0], Cst->front()); in buildInstr()
234 return buildConstant(DstOps[0], *Cst); in buildInstr()
265 return buildConstant(Dst, *MaybeCst); in buildInstr()
291 return buildConstant(DstOps[0], (*MaybeCsts)[0]); in buildInstr()
297 buildConstant(VecTy.getScalarType(), Cst).getReg(0)); in buildInstr()
328 MachineInstrBuilder CSEMIRBuilder::buildConstant(const DstOp &Res, in buildConstant() function in CSEMIRBuilder
332 return MachineIRBuilder::buildConstant(Res, Val); in buildConstant()
337 return buildSplatBuildVector(Res, buildConstant(Ty.getElementType(), Val)); in buildConstant()
351 MachineInstrBuilder NewMIB = MachineIRBuilder::buildConstant(Res, Val); in buildConstant()
H A DCombinerHelper.cpp86 auto Base = MIB.buildConstant(Ty, Ty.getScalarSizeInBits() - 1); in buildLogBase2()
1453 auto NewCst = Builder.buildConstant(MRI.getType(MatchInfo.Offset), in applyCombineIndexedLoadStore()
1614 auto True = Builder.buildConstant( in applyOptBrCondByInvertingCond()
1768 auto NewOffset = MIB.buildConstant(OffsetTy, MatchInfo.Imm); in applyPtrAddImmedChain()
1836 Builder.buildConstant(MI.getOperand(0), 0); in applyShiftImmedChain()
1846 Register NewImm = Builder.buildConstant(ImmTy, Imm).getReg(0); in applyShiftImmedChain()
1945 Register Const = Builder.buildConstant(ShlType, MatchInfo.ValSum).getReg(0); in applyShiftOfShiftedLogic()
2025 auto ShiftCst = MIB.buildConstant(ShiftTy, ShiftVal); in applyCombineMulToShl()
2079 auto ShiftAmt = Builder.buildConstant(ExtSrcTy, ShiftAmtVal); in applyCombineShlOfExtend()
2202 Builder.buildConstant(DstReg, Csts[Idx]); in applyCombineUnmergeConstant()
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H A DMachineIRBuilder.cpp223 auto Cst = buildConstant(ValueTy, Value); in materializePtrAdd()
233 buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits)); in buildMaskLowPtrBits()
317 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, in buildConstant() function in MachineIRBuilder
341 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, in buildConstant() function in MachineIRBuilder
346 return buildConstant(Res, *CI); in buildConstant()
378 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, in buildConstant() function in MachineIRBuilder
381 return buildConstant(Res, *CI); in buildConstant()
463 auto ConstOffset = buildConstant(OffsetTy, Offset); in buildLoadFromOffset()
590 auto Mask = buildConstant( in buildZExtInReg()
726 TmpVec.push_back(buildConstant(EltTy, Op)); in buildBuildVectorConstant()
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H A DIRTranslator.cpp864 auto FirstCst = MIB.buildConstant(SwitchTy, JTH.First); in emitJumpTableHeader()
952 auto Diff = MIB.buildConstant(CmpTy, High - Low); in emitSwitchCase()
1091 Register MinValReg = MIB.buildConstant(SwitchOpTy, B.First).getReg(0); in emitBitTestHeader()
1129 auto RangeCst = MIB.buildConstant(SwitchOpTy, B.Range); in emitBitTestHeader()
1155 MIB.buildConstant(SwitchTy, llvm::countr_zero(B.Mask)); in emitBitTestCase()
1162 MIB.buildConstant(SwitchTy, llvm::countr_one(B.Mask)); in emitBitTestCase()
1167 auto CstOne = MIB.buildConstant(SwitchTy, 1); in emitBitTestCase()
1171 auto CstMask = MIB.buildConstant(SwitchTy, B.Mask); in emitBitTestCase()
1173 auto CstZero = MIB.buildConstant(SwitchTy, 0); in emitBitTestCase()
1634 auto OffsetMIB = MIRBuilder.buildConstant({OffsetTy}, Offset); in translateGetElementPtr()
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H A DLoadStoreOpt.cpp415 WideReg = Builder.buildConstant(WideValueTy, WideConst).getReg(0); in doSingleStoreMerge()
890 Builder.buildConstant(WideStoreTy, WideStoreTy.getSizeInBits() / 2); in mergeTruncStore()
H A DCombinerHelperVectorOps.cpp375 auto Idx = B.buildConstant(IdxTy, SrcIdx); in matchExtractVectorElementWithShuffleVector()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp528 auto ExtCst = MIRBuilder.buildConstant(LLT::scalar(64), Amount); in legalizeShlAshrLshr()
606 MIB.buildLShr(Dst, VLENB, MIB.buildConstant(XLenTy, 3 - Log2)); in legalizeVScale()
609 MIB.buildShl(Dst, VLENB, MIB.buildConstant(XLenTy, Log2 - 3)); in legalizeVScale()
617 MIB.buildMul(Dst, VLENB, MIB.buildConstant(XLenTy, Val / 8)); in legalizeVScale()
620 auto VScale = MIB.buildLShr(XLenTy, VLENB, MIB.buildConstant(XLenTy, 3)); in legalizeVScale()
621 MIB.buildMul(Dst, VScale, MIB.buildConstant(XLenTy, Val)); in legalizeVScale()
645 auto SplatZero = MIB.buildSplatVector(DstTy, MIB.buildConstant(DstEltTy, 0)); in legalizeExt()
647 MIB.buildSplatVector(DstTy, MIB.buildConstant(DstEltTy, ExtTrueVal)); in legalizeExt()
757 MIB.buildAnd(InterEltTy, ZExtSplatVal, MIB.buildConstant(InterEltTy, 1)); in legalizeSplatVector()
760 MIB.buildSplatVector(InterTy, MIB.buildConstant(InterEltTy, 0)); in legalizeSplatVector()
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H A DRISCVCallLowering.cpp80 auto OffsetReg = MIRBuilder.buildConstant(sXLen, Offset); in getStackAddress()
479 auto Offset = MIRBuilder.buildConstant( in saveVarArgRegisters()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp119 auto Elt0 = B.buildExtractVectorElement(Ty, Src, B.buildConstant(s64, 0)); in applyExtractVecEltPairwiseAdd()
120 auto Elt1 = B.buildExtractVectorElement(Ty, Src, B.buildConstant(s64, 1)); in applyExtractVecEltPairwiseAdd()
226 auto Shift = B.buildConstant(LLT::scalar(64), ShiftAmt); in matchAArch64MulConstCombine()
236 B.buildSub(DstReg, B.buildConstant(Ty, 0), Res); in matchAArch64MulConstCombine()
241 B.buildShl(DstReg, Res, B.buildConstant(LLT::scalar(64), TrailingZeroes)); in matchAArch64MulConstCombine()
334 auto Zero = B.buildConstant(NewTy, 0); in applySplitStoreZero128()
336 B.buildConstant(LLT::scalar(64), 8)); in applySplitStoreZero128()
430 Register ZeroVec = B.buildConstant(HalfTy, 0).getReg(0); in applyCombineMulCMLT()
605 auto NewOff = MIB.buildConstant(LLT::scalar(64), SInfo.Offset - BaseOffset); in tryOptimizeConsecStores()
H A DAArch64PreLegalizerCombiner.cpp69 MIB.buildConstant(MI.getOperand(0).getReg(), ImmValAPF.bitcastToAPInt()); in applyFConstantToConstant()
114 auto WideZero = Builder.buildConstant(WideTy, 0); in applyICmpRedundantTrunc()
229 B.buildConstant(LLT::scalar(64), -static_cast<int64_t>(MinOffset))); in applyFoldGlobalOffset()
308 Ext2SrcReg = Builder.buildConstant(MRI.getType(Ext1SrcReg), 1) in applyExtAddvToUdotAddv()
330 auto Zeroes = Builder.buildConstant(MidTy, 0)->getOperand(0).getReg(); in applyExtAddvToUdotAddv()
355 Register v8Zeroes = Builder.buildConstant(LLT::fixed_vector(8, 8), 0) in applyExtAddvToUdotAddv()
392 auto Zeroes = Builder.buildConstant(ZeroesLLT, 0)->getOperand(0).getReg(); in applyExtAddvToUdotAddv()
494 Register zeroReg = B.buildConstant(LLT::scalar(64), 0).getReg(0); in applyExtUaddvToUaddlv()
702 B.buildConstant(LLT::scalar(32), OpTySize == 8 ? 1 << 8 : 1 << 16)); in tryToSimplifyUADDO()
704 B.buildConstant(LLT::scalar(32), 0)); in tryToSimplifyUADDO()
H A DAArch64PostLegalizerLowering.cpp398 MIRBuilder.buildConstant(LLT::scalar(32), MatchInfo.SrcOps[2].getImm()); in applyEXT()
439 auto Mask = Builder.buildConstant(IdxTy, VecTy.getNumElements() - 1); in applyNonConstInsert()
441 auto EltSize = Builder.buildConstant(IdxTy, EltTy.getSizeInBytes()); in applyNonConstInsert()
501 auto SrcCst = Builder.buildConstant(LLT::scalar(64), SrcLane); in applyINS()
503 auto DstCst = Builder.buildConstant(LLT::scalar(64), DstLane); in applyINS()
541 auto ImmDef = MIB.buildConstant(LLT::scalar(32), Imm); in applyVAshrLshrImm()
681 auto Cst = MIB.buildConstant(MRI.cloneVirtualRegister(RHS.getReg()), in applyAdjustICmpImmAndPred()
752 auto Lane = B.buildConstant(LLT::scalar(64), MatchInfo.second); in applyDupLane()
H A DAArch64LegalizerInfo.cpp1387 auto Cast64 = MIRBuilder.buildConstant(LLT::scalar(64), Amount.zext(64)); in legalizeFunnelShift()
1539 MIB.buildConstant(MI.getOperand(0).getReg(), 0); in legalizeIntrinsic()
1637 MIB.buildConstant(LLT::scalar(64), 0)->getOperand(0).getReg(); in legalizeIntrinsic()
1707 auto ExtCst = MIRBuilder.buildConstant(LLT::scalar(64), Amount); in legalizeShlAshrLshr()
1844 MIRBuilder.buildConstant(IntPtrTy, Alignment.value() - 1); in legalizeVaArg()
1857 auto Size = MIRBuilder.buildConstant(IntPtrTy, alignTo(ValSize, PtrAlign)); in legalizeVaArg()
1951 auto Zeros = MIRBuilder.buildConstant(Dt, 0); in legalizeCTPOP()
1952 auto Ones = MIRBuilder.buildConstant(VTy, 1); in legalizeCTPOP()
H A DAArch64CallLowering.cpp273 auto OffsetReg = MIRBuilder.buildConstant(s64, Offset); in getStackAddress()
586 MIRBuilder.buildConstant(MRI.createGenericVirtualRegister(s64), 8); in saveVarArgRegisters()
616 MIRBuilder.buildConstant(MRI.createGenericVirtualRegister(s64), 16); in saveVarArgRegisters()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCSEMIRBuilder.h98 using MachineIRBuilder::buildConstant;
100 MachineInstrBuilder buildConstant(const DstOp &Res,
H A DLegalizationArtifactCombiner.h108 Builder.buildConstant( in tryCombineAnyExt()
158 auto Mask = Builder.buildConstant(DstTy, ExtMaskVal); in tryCombineZExt()
183 Builder.buildConstant( in tryCombineZExt()
247 Builder.buildConstant( in tryCombineSExt()
275 Builder.buildConstant( in tryCombineTrunc()
403 Builder.buildConstant(DstReg, 0); in tryFoldImplicitDef()
H A DMachineIRBuilder.h860 virtual MachineInstrBuilder buildConstant(const DstOp &Res,
871 MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
872 MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
1353 Res, Val, buildConstant(LLT::scalar(VecIdxWidth), Idx)); in buildExtractVectorElementConstant()
1821 auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1); in buildNot()
1829 auto Zero = buildConstant(Dst.getLLTTy(*getMRI()), 0); in buildNeg()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2251 B.buildConstant(LLT::scalar(64), Offset).getReg(0)); in getSegmentAperture()
2273 B.buildConstant(LLT::scalar(64), StructOffset).getReg(0)); in getSegmentAperture()
2344 auto SegmentNull = B.buildConstant(DstTy, NullVal); in legalizeAddrSpaceCast()
2345 auto FlatNull = B.buildConstant(SrcTy, 0); in legalizeAddrSpaceCast()
2380 auto SegmentNull = B.buildConstant(SrcTy, TM.getNullPointerValue(SrcAS)); in legalizeAddrSpaceCast()
2381 auto FlatNull = B.buildConstant(DstTy, TM.getNullPointerValue(DestAS)); in legalizeAddrSpaceCast()
2405 auto HighAddr = B.buildConstant(S32, AddrHiVal); in legalizeAddrSpaceCast()
2499 auto Const0 = B.buildConstant(S32, FractBits - 32); in extractF64Exponent()
2500 auto Const1 = B.buildConstant(S32, ExpBits); in extractF64Exponent()
2507 return B.buildSub(S32, ExpPart, B.buildConstant(S32, 1023)); in extractF64Exponent()
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H A DAMDGPURegisterBankInfo.cpp142 auto True = B.buildConstant(S32, Opc == AMDGPU::G_SEXT ? -1 : 1); in applyBank()
143 auto False = B.buildConstant(S32, 0); in applyBank()
1200 auto WaveSize = B.buildConstant(LLT::scalar(32), ST.getWavefrontSizeLog2()); in applyMappingDynStackAlloc()
1256 VOffsetReg = B.buildConstant(S32, 0).getReg(0); in setBufferOffsets()
1257 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0); in setBufferOffsets()
1277 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0); in setBufferOffsets()
1285 VOffsetReg = B.buildConstant(S32, 0).getReg(0); in setBufferOffsets()
1324 SOffsetReg = B.buildConstant(S32, 0).getReg(0); in setBufferOffsets()
1385 Register VIndex = B.buildConstant(S32, 0).getReg(0); in applyMappingSBufferLoad()
1487 auto Zero = B.buildConstant(S32, 0); in applyMappingBFE()
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H A DAMDGPUPreLegalizerCombiner.cpp196 auto MinBoundaryDst = B.buildConstant(S32, MinBoundary); in applyClampI64ToI16()
197 auto MaxBoundaryDst = B.buildConstant(S32, MaxBoundary); in applyClampI64ToI16()
H A DAMDGPUCallLowering.cpp226 auto OffsetReg = MIRBuilder.buildConstant(S32, Offset); in getStackAddress()
409 auto OffsetReg = B.buildConstant(LLT::scalar(64), Offset); in lowerParameterPtr()
830 MIRBuilder.buildConstant(InputReg, *Id); in passSpecialInputs()
893 InputReg = MIRBuilder.buildConstant(S32, 0).getReg(0); in passSpecialInputs()
903 Y = MIRBuilder.buildShl(S32, Y, MIRBuilder.buildConstant(S32, 10)).getReg(0); in passSpecialInputs()
913 Z = MIRBuilder.buildShl(S32, Z, MIRBuilder.buildConstant(S32, 20)).getReg(0); in passSpecialInputs()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLegalizerInfo.cpp388 MIRBuilder.buildConstant(OriginalResult, in legalizeCustom()
426 auto Zero = MIRBuilder.buildConstant(LLT::scalar(32), 0); in legalizeCustom()
442 MIRBuilder.buildConstant(MI.getOperand(0), in legalizeCustom()
452 auto StatusBitMask = MIRBuilder.buildConstant(FPEnvTy, ARM::FPStatusBits); in legalizeCustom()
455 MIRBuilder.buildConstant(FPEnvTy, ~ARM::FPStatusBits); in legalizeCustom()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsLegalizerInfo.cpp380 auto C_P2HalfMemSize = MIRBuilder.buildConstant(s32, P2HalfMemSize); in legalizeCustom()
385 auto C_P2Half_InBits = MIRBuilder.buildConstant(s32, P2HalfMemSize * 8); in legalizeCustom()
409 auto C_P2HalfMemSize = MIRBuilder.buildConstant(s32, P2HalfMemSize); in legalizeCustom()
445 auto C_HiMask = MIRBuilder.buildConstant(s32, UINT32_C(0x43300000)); in legalizeCustom()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp84 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); in getStackAddress()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallLowering.cpp

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