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Searched refs:buildAnd (Results 1 – 16 of 16) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegBankLegalizeHelper.cpp176 auto Lo = B.buildAnd(SgprRB_S32, PackedS32, Mask); in unpackZExt()
306 auto FieldOffset = B.buildAnd(SgprRB_S32, LSBit, Mask); in lowerS_BFE()
456 auto AndLo = B.buildAnd(VgprRB_S32, Src64.getReg(0), One); in lower()
458 auto AndHi = B.buildAnd(VgprRB_S32, Src64.getReg(1), Zero); in lower()
463 B.buildAnd(BoolSrc, Src, One); in lower()
943 auto BoolInReg = B.buildAnd(SgprRB_S32, Aext, Cst1); in applyMappingSrc()
H A DAMDGPURegBankLegalize.cpp161 auto BoolSrc = B.buildAnd({SgprRB, S32}, TruncS32Src, One); in tryCombineCopy()
H A DAMDGPURegBankCombiner.cpp386 auto And = B.buildAnd(ExtAmtTy, NewExt, Mask); in applyCanonicalizeZextShiftAmt()
H A DAMDGPULegalizerInfo.cpp2517 auto And = B.buildAnd(S1, Lt0, NeTrunc); in legalizeFceil()
2582 auto SignBit = B.buildAnd(S32, Hi, SignBitMask); in legalizeIntrinsicTrunc()
2593 auto Tmp0 = B.buildAnd(S64, Src, Not); in legalizeIntrinsicTrunc()
3470 auto YH = B.buildAnd(Ty, Y, MaskConst); in legalizeFlogCommon()
3737 auto XH = B.buildAnd(Ty, X, MaskConst); in legalizeFExp()
4343 B.buildAnd(DstReg, AndMaskSrc, B.buildConstant(S32, Mask >> Shift)); in buildLoadInputValue()
4979 Tmp = B.buildAnd(S32, Tmp, B.buildConstant(S32, 0xff800000)); in legalizeFDIV16()
5684 auto Masked = B.buildAnd(S32, HighHalf, AndMask); in legalizePointerAsRsrcIntrin()
H A DAMDGPURegisterBankInfo.cpp924 CondReg = B.buildAnd(S1, CondReg, CmpReg).getReg(0); in executeInWaterfallLoop()
1558 auto ClampOffset = B.buildAnd(S32, OffsetReg, OffsetMask); in applyMappingBFE()
1761 auto ExtLo = B.buildAnd(S32, Bitcast, B.buildConstant(S32, 0xffff)); in unpackV2S16ToS32()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp1201 MIRBuilder.buildAnd(DstReg, NotOeq, NotUno); in createFCMPLibcall()
3626 auto OffsetIdx = B.buildAnd(IdxTy, Idx, OffsetMask); in getBitcastWiderVectorElementOffset()
3761 auto MaskedOldElt = B.buildAnd(TargetTy, TargetReg, InvShiftedMask); in buildBitFieldInsert()
4605 auto Carry2 = MIRBuilder.buildAnd(CondTy, ResEqZero, CarryIn); in lower()
4642 auto Borrow2 = MIRBuilder.buildAnd(CondTy, TmpResEqZero, BorrowIn); in lower()
4832 return B.buildAnd(IdxTy, IdxReg, B.buildConstant(IdxTy, Imm)).getReg(0); in clampVectorIndex()
7174 auto MIBTmp = MIRBuilder.buildAnd( in lowerBitCount()
7205 auto B2Count1Hi = B.buildAnd(Ty, B2Set1LoTo1Hi, C_B2Mask1HiTo0); in lowerBitCount()
7214 auto B4HiB2Count = B.buildAnd(Ty, B4Set2LoTo2Hi, C_B4Mask2HiTo0); in lowerBitCount()
7215 auto B4LoB2Count = B.buildAnd(Ty, B2Count, C_B4Mask2HiTo0); in lowerBitCount()
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H A DCombinerHelper.cpp3309 B.buildAnd(Dst, R, B.buildConstant(Ty, C1 & C2)); in matchOverlappingAnd()
3732 Builder.buildAnd(DstReg, Src0, Add); in applySimplifyURemByPow2()
5707 T = MIB.buildAnd(Ty, T, ShiftMask); in buildSDivUsingMul()
7162 B.buildAnd(DstReg, Ext, FreezeTrue); in tryFoldBoolSelectToLogic()
7194 B.buildAnd(DstReg, Ext, FreezeFalse); in tryFoldBoolSelectToLogic()
7448 auto And = B.buildAnd(CmpOperandTy, R1, TildeLowerDiff); // the mask. in tryFoldAndOrOrICmpsUsingRanges()
7456 auto And = B.buildAnd(CmpOperandTy, R1, TildeLowerDiff); // the mask. in tryFoldAndOrOrICmpsUsingRanges()
H A DMachineIRBuilder.cpp594 return buildAnd(Res, Op, Mask); in buildZExtInReg()
H A DIRTranslator.cpp1186 auto AndOp = MIB.buildAnd(SwitchTy, SwitchVal, CstMask); in emitBitTestCase()
3122 auto AlignedAlloc = MIRBuilder.buildAnd(IntPtrTy, AllocAdd, AlignCst); in translateAlloca()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLegalizerInfo.cpp463 auto StatusBits = MIRBuilder.buildAnd(FPEnvTy, FPEnv, StatusBitMask); in legalizeCustom()
466 auto FPModeBits = MIRBuilder.buildAnd(FPEnvTy, Modes, NotStatusBitMask); in legalizeCustom()
478 auto NewFPSCR = MIRBuilder.buildAnd(FPEnvTy, FPEnv, NotModeBitMask); in legalizeCustom()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86LegalizerInfo.cpp843 s32, MIRBuilder.buildAnd(s8, Shifted8, MIRBuilder.buildConstant(s8, 6))); in legalizeGETROUNDING()
852 MIRBuilder.buildAnd(s32, LUTShifted, MIRBuilder.buildConstant(s32, 3)); in legalizeGETROUNDING()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp1052 MIB.buildAnd(InterEltTy, ZExtSplatVal, MIB.buildConstant(InterEltTy, 1)); in legalizeSplatVector()
1444 auto And = MIB.buildAnd(sXLen, GFClass, FClassMask); in legalizeCustom()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PreLegalizerCombiner.cpp700 B.buildAnd( in tryToSimplifyUADDO()
H A DAArch64PostLegalizerLowering.cpp458 Register And = Builder.buildAnd(IdxTy, Offset, Mask).getReg(0); in applyNonConstInsert()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h159 Builder.buildAnd(DstReg, AndSrc, Mask); in tryCombineZExt()
H A DMachineIRBuilder.h1959 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, in buildAnd() function